bzr branch
http://bzr.ed.am/elec/quadcopter
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1 |
(kicad_pcb (version 3) (host pcbnew "(2013-jul-07)-stable") |
2 |
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3 |
(general |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
4 |
(links 98) |
5 |
(no_connects 6) |
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6 |
(area 25.070999 45.390999 76.529001 126.059001) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
7 |
(thickness 1.6) |
8 |
(drawings 0) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
9 |
(tracks 251) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
10 |
(zones 0) |
11 |
(modules 33) |
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12 |
(nets 26) |
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13 |
) |
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14 |
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15 |
(page A3) |
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16 |
(layers |
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17 |
(15 F.Cu signal) |
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18 |
(0 B.Cu signal) |
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19 |
(16 B.Adhes user) |
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20 |
(17 F.Adhes user) |
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21 |
(18 B.Paste user) |
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22 |
(19 F.Paste user) |
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23 |
(20 B.SilkS user) |
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24 |
(21 F.SilkS user) |
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25 |
(22 B.Mask user) |
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26 |
(23 F.Mask user) |
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27 |
(24 Dwgs.User user) |
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28 |
(25 Cmts.User user) |
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29 |
(26 Eco1.User user) |
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30 |
(27 Eco2.User user) |
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31 |
(28 Edge.Cuts user) |
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32 |
) |
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33 |
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34 |
(setup |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
35 |
(last_trace_width 0.381) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
36 |
(trace_clearance 0.254) |
37 |
(zone_clearance 0.508) |
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38 |
(zone_45_only no) |
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39 |
(trace_min 0.254) |
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40 |
(segment_width 0.2) |
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41 |
(edge_width 0.15) |
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42 |
(via_size 0.889) |
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43 |
(via_drill 0.635) |
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44 |
(via_min_size 0.889) |
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45 |
(via_min_drill 0.508) |
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46 |
(uvia_size 0.508) |
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47 |
(uvia_drill 0.127) |
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48 |
(uvias_allowed no) |
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49 |
(uvia_min_size 0.508) |
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50 |
(uvia_min_drill 0.127) |
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51 |
(pcb_text_width 0.3) |
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52 |
(pcb_text_size 1.5 1.5) |
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53 |
(mod_edge_width 0.15) |
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54 |
(mod_text_size 1.5 1.5) |
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55 |
(mod_text_width 0.15) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
56 |
(pad_size 2.032 1.524) |
57 |
(pad_drill 1.143) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
58 |
(pad_to_mask_clearance 0.2) |
59 |
(aux_axis_origin 0 0) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
60 |
(visible_elements FFFE3FBF) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
61 |
(pcbplotparams |
62 |
(layerselection 3178497) |
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63 |
(usegerberextensions true) |
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64 |
(excludeedgelayer true) |
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65 |
(linewidth 0.100000) |
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66 |
(plotframeref false) |
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67 |
(viasonmask false) |
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68 |
(mode 1) |
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69 |
(useauxorigin false) |
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70 |
(hpglpennumber 1) |
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71 |
(hpglpenspeed 20) |
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72 |
(hpglpendiameter 15) |
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73 |
(hpglpenoverlay 2) |
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74 |
(psnegative false) |
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75 |
(psa4output false) |
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76 |
(plotreference true) |
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77 |
(plotvalue true) |
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78 |
(plotothertext true) |
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79 |
(plotinvisibletext false) |
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80 |
(padsonsilk false) |
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81 |
(subtractmaskfromsilk false) |
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82 |
(outputformat 1) |
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83 |
(mirror false) |
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84 |
(drillshape 1) |
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85 |
(scaleselection 1) |
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86 |
(outputdirectory "")) |
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87 |
) |
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88 |
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89 |
(net 0 "") |
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90 |
(net 1 /GND) |
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91 |
(net 2 /VCC) |
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92 |
(net 3 N-000001) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
93 |
(net 4 N-0000017) |
94 |
(net 5 N-0000018) |
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95 |
(net 6 N-0000019) |
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96 |
(net 7 N-000002) |
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97 |
(net 8 N-0000020) |
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98 |
(net 9 N-0000021) |
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99 |
(net 10 N-0000022) |
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100 |
(net 11 N-0000023) |
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101 |
(net 12 N-0000024) |
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102 |
(net 13 N-0000025) |
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103 |
(net 14 N-0000026) |
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104 |
(net 15 N-000003) |
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105 |
(net 16 N-0000034) |
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106 |
(net 17 N-000004) |
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107 |
(net 18 N-0000048) |
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108 |
(net 19 N-000005) |
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109 |
(net 20 N-0000050) |
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110 |
(net 21 N-0000052) |
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111 |
(net 22 N-0000054) |
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112 |
(net 23 N-0000060) |
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113 |
(net 24 N-0000079) |
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114 |
(net 25 N-0000080) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
115 |
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116 |
(net_class Default "This is the default net class." |
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117 |
(clearance 0.254) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
118 |
(trace_width 0.381) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
119 |
(via_dia 0.889) |
120 |
(via_drill 0.635) |
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121 |
(uvia_dia 0.508) |
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122 |
(uvia_drill 0.127) |
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123 |
(add_net "") |
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124 |
(add_net /GND) |
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125 |
(add_net /VCC) |
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126 |
(add_net N-000001) |
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127 |
(add_net N-0000017) |
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128 |
(add_net N-0000018) |
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129 |
(add_net N-0000019) |
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130 |
(add_net N-000002) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
131 |
(add_net N-0000020) |
132 |
(add_net N-0000021) |
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133 |
(add_net N-0000022) |
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134 |
(add_net N-0000023) |
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135 |
(add_net N-0000024) |
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136 |
(add_net N-0000025) |
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137 |
(add_net N-0000026) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
138 |
(add_net N-000003) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
139 |
(add_net N-0000034) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
140 |
(add_net N-000004) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
141 |
(add_net N-0000048) |
142 |
(add_net N-000005) |
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143 |
(add_net N-0000050) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
144 |
(add_net N-0000052) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
145 |
(add_net N-0000054) |
146 |
(add_net N-0000060) |
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147 |
(add_net N-0000079) |
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148 |
(add_net N-0000080) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
149 |
) |
150 |
||
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
151 |
(module R3 (layer F.Cu) (tedit 534C7795) (tstamp 5345C6FF) |
152 |
(at 35.56 93.98 90) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
153 |
(descr "Resitance 3 pas") |
154 |
(tags R) |
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155 |
(path /5320CEF3) |
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156 |
(autoplace_cost180 10) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
157 |
(fp_text reference R1 (at 0 0.127 90) (layer F.SilkS) hide |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
158 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
159 |
) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
160 |
(fp_text value 20K (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
161 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
162 |
) |
|
163 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
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164 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
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165 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
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166 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
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167 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
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168 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
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169 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
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170 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
171 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
172 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
173 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
174 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
175 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
176 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
177 |
(net 24 N-0000079) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
178 |
) |
179 |
(model discret/resistor.wrl |
|
180 |
(at (xyz 0 0 0)) |
|
181 |
(scale (xyz 0.3 0.3 0.3)) |
|
182 |
(rotate (xyz 0 0 0)) |
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183 |
) |
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184 |
) |
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185 |
||
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
186 |
(module R3 (layer F.Cu) (tedit 534C956E) (tstamp 5345CB8B) |
187 |
(at 38.1 93.98 270) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
188 |
(descr "Resitance 3 pas") |
189 |
(tags R) |
|
190 |
(path /5320CF02) |
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191 |
(autoplace_cost180 10) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
192 |
(fp_text reference R2 (at 0 0.127 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
193 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
194 |
) |
|
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
195 |
(fp_text value 10K (at 0 0.127 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
196 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
197 |
) |
|
198 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
199 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
200 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
201 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
202 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
203 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
204 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
205 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
206 |
(pad 1 thru_hole circle (at -3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
207 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
208 |
(net 24 N-0000079) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
209 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
210 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
211 |
(layers *.Cu *.Mask F.SilkS) |
212 |
(net 1 /GND) |
|
213 |
) |
|
214 |
(model discret/resistor.wrl |
|
215 |
(at (xyz 0 0 0)) |
|
216 |
(scale (xyz 0.3 0.3 0.3)) |
|
217 |
(rotate (xyz 0 0 0)) |
|
218 |
) |
|
219 |
) |
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220 |
||
221 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C718) |
|
222 |
(at 39.37 58.42 90) |
|
223 |
(path /5321281E) |
|
224 |
(attr virtual) |
|
225 |
(fp_text reference P5 (at -1.905 -3.81 90) (layer F.SilkS) |
|
226 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
227 |
) |
|
228 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
229 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
230 |
) |
|
231 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
232 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
233 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
234 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
235 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
236 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
237 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
238 |
(net 2 /VCC) |
|
239 |
) |
|
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
240 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
241 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
242 |
(net 1 /GND) |
|
243 |
) |
|
244 |
) |
|
245 |
||
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
246 |
(module PINHEAD1-2 (layer F.Cu) (tedit 534C790C) (tstamp 534C7AD5) |
247 |
(at 35.56 119.38 180) |
|
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
248 |
(path /53212E1B) |
249 |
(attr virtual) |
|
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
250 |
(fp_text reference P1 (at -1.905 -3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
251 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
252 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
253 |
(fp_text value CONN_2 (at 0 3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
254 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
255 |
) |
|
256 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
257 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
258 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
259 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
260 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
261 |
(pad 1 thru_hole oval (at -1.27 0 180) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
262 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
263 |
(net 1 /GND) |
|
264 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
265 |
(pad 2 thru_hole oval (at 1.27 0 180) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
266 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
267 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
268 |
) |
269 |
) |
|
270 |
||
271 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C739) |
|
272 |
(at 69.85 58.42 90) |
|
273 |
(path /532128A9) |
|
274 |
(attr virtual) |
|
275 |
(fp_text reference P13 (at -1.905 -3.81 90) (layer F.SilkS) |
|
276 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
277 |
) |
|
278 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
279 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
280 |
) |
|
281 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
282 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
283 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
284 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
285 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
286 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
287 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
288 |
(net 2 /VCC) |
|
289 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
290 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
291 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
292 |
(net 1 /GND) |
|
293 |
) |
|
294 |
) |
|
295 |
||
296 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C744) |
|
297 |
(at 62.23 58.42 90) |
|
298 |
(path /5321289A) |
|
299 |
(attr virtual) |
|
300 |
(fp_text reference P11 (at -1.905 -3.81 90) (layer F.SilkS) |
|
301 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
302 |
) |
|
303 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
304 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
305 |
) |
|
306 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
307 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
308 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
309 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
310 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
311 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
312 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
313 |
(net 2 /VCC) |
|
314 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
315 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
316 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
317 |
(net 1 /GND) |
|
318 |
) |
|
319 |
) |
|
320 |
||
321 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C74F) |
|
322 |
(at 54.61 58.42 90) |
|
323 |
(path /5321288B) |
|
324 |
(attr virtual) |
|
325 |
(fp_text reference P9 (at -1.905 -3.81 90) (layer F.SilkS) |
|
326 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
327 |
) |
|
328 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
329 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
330 |
) |
|
331 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
332 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
333 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
334 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
335 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
336 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
337 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
338 |
(net 2 /VCC) |
|
339 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
340 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
341 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
342 |
(net 1 /GND) |
|
343 |
) |
|
344 |
) |
|
345 |
||
346 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C75A) |
|
347 |
(at 46.99 58.42 90) |
|
348 |
(path /5321287C) |
|
349 |
(attr virtual) |
|
350 |
(fp_text reference P7 (at -1.905 -3.81 90) (layer F.SilkS) |
|
351 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
352 |
) |
|
353 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
354 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
355 |
) |
|
356 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
357 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
358 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
359 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
360 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
361 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
362 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
363 |
(net 2 /VCC) |
|
364 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
365 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
366 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
367 |
(net 1 /GND) |
|
368 |
) |
|
369 |
) |
|
370 |
||
371 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C765) |
|
372 |
(at 31.75 58.42 90) |
|
373 |
(path /5321280F) |
|
374 |
(attr virtual) |
|
375 |
(fp_text reference P3 (at -1.905 -3.81 90) (layer F.SilkS) |
|
376 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
377 |
) |
|
378 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
379 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
380 |
) |
|
381 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
382 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
383 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
384 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
385 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
386 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
387 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
388 |
(net 2 /VCC) |
|
389 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
390 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
391 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
392 |
(net 1 /GND) |
|
393 |
) |
|
394 |
) |
|
395 |
||
396 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C770) |
|
397 |
(at 69.85 50.8 90) |
|
398 |
(path /53212800) |
|
399 |
(attr virtual) |
|
400 |
(fp_text reference P14 (at -1.905 -3.81 90) (layer F.SilkS) |
|
401 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
402 |
) |
|
403 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
404 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
405 |
) |
|
406 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
407 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
408 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
409 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
410 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
411 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
412 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
413 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
414 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
415 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
416 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
417 |
(net 1 /GND) |
|
418 |
) |
|
419 |
) |
|
420 |
||
421 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C77B) |
|
422 |
(at 62.23 50.8 90) |
|
423 |
(path /532127F1) |
|
424 |
(attr virtual) |
|
425 |
(fp_text reference P12 (at -1.905 -3.81 90) (layer F.SilkS) |
|
426 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
427 |
) |
|
428 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
429 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
430 |
) |
|
431 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
432 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
433 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
434 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
435 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
436 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
437 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
438 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
439 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
440 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
441 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
442 |
(net 1 /GND) |
|
443 |
) |
|
444 |
) |
|
445 |
||
446 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C786) |
|
447 |
(at 54.61 50.8 90) |
|
448 |
(path /532127E2) |
|
449 |
(attr virtual) |
|
450 |
(fp_text reference P10 (at -1.905 -3.81 90) (layer F.SilkS) |
|
451 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
452 |
) |
|
453 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
454 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
455 |
) |
|
456 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
457 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
458 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
459 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
460 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
461 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
462 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
463 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
464 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
465 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
466 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
467 |
(net 1 /GND) |
|
468 |
) |
|
469 |
) |
|
470 |
||
471 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C791) |
|
472 |
(at 46.99 50.8 90) |
|
473 |
(path /532127D3) |
|
474 |
(attr virtual) |
|
475 |
(fp_text reference P8 (at -1.905 -3.81 90) (layer F.SilkS) |
|
476 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
477 |
) |
|
478 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
479 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
480 |
) |
|
481 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
482 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
483 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
484 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
485 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
486 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
487 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
488 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
489 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
490 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
491 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
492 |
(net 1 /GND) |
|
493 |
) |
|
494 |
) |
|
495 |
||
496 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C79C) |
|
497 |
(at 39.37 50.8 90) |
|
498 |
(path /532127B5) |
|
499 |
(attr virtual) |
|
500 |
(fp_text reference P6 (at -1.905 -3.81 90) (layer F.SilkS) |
|
501 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
502 |
) |
|
503 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
504 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
505 |
) |
|
506 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
507 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
508 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
509 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
510 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
511 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
512 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
513 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
514 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
515 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
516 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
517 |
(net 1 /GND) |
|
518 |
) |
|
519 |
) |
|
520 |
||
521 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C7A7) |
|
522 |
(at 31.75 50.8 90) |
|
523 |
(path /53212777) |
|
524 |
(attr virtual) |
|
525 |
(fp_text reference P4 (at -1.905 -3.81 90) (layer F.SilkS) |
|
526 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
527 |
) |
|
528 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
529 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
530 |
) |
|
531 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
532 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
533 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
534 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
535 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
536 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
537 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
538 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
539 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
540 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
541 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
542 |
(net 1 /GND) |
|
543 |
) |
|
544 |
) |
|
545 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
546 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534C7F7E) (tstamp 534C7FE8) |
547 |
(at 68.58 68.58 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
548 |
(descr "Double rangee de contacts 2 x 5 pins") |
549 |
(tags CONN) |
|
550 |
(path /53497310) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
551 |
(fp_text reference P2 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
552 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
553 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
554 |
(fp_text value HC-SR04_PROXSENS (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
555 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
556 |
) |
|
557 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
558 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
559 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
560 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
561 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
562 |
(layers *.Cu *.Mask F.SilkS) |
563 |
(net 2 /VCC) |
|
564 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
565 |
(pad 2 thru_hole oval (at -1.27 0 270) (size 1.524 2.286) (drill 1.143) |
566 |
(layers *.Cu *.Mask F.SilkS) |
|
567 |
(net 18 N-0000048) |
|
568 |
) |
|
569 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
570 |
(layers *.Cu *.Mask F.SilkS) |
|
571 |
(net 21 N-0000052) |
|
572 |
) |
|
573 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
574 |
(layers *.Cu *.Mask F.SilkS) |
575 |
(net 1 /GND) |
|
576 |
) |
|
577 |
(model pin_array\pins_array_4x1.wrl |
|
578 |
(at (xyz 0 0 0)) |
|
579 |
(scale (xyz 1 1 1)) |
|
580 |
(rotate (xyz 0 0 0)) |
|
581 |
) |
|
582 |
) |
|
583 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
584 |
(module IMU_Mount (layer F.Cu) (tedit 534C96DF) (tstamp 5345C7DA) |
585 |
(at 43.18 93.98) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
586 |
(path /532A16AB) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
587 |
(fp_text reference U1 (at 0 -2.54) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
588 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
589 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
590 |
(fp_text value IMU_MOUNT (at 0 0) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
591 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
592 |
) |
|
593 |
(fp_line (start -12.7 8.89) (end 12.7 8.89) (layer F.SilkS) (width 0.15)) |
|
594 |
(fp_line (start -12.7 8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
595 |
(fp_line (start 12.7 8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
596 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
597 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
598 |
(fp_line (start 12.7 -8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
599 |
(pad 1 thru_hole circle (at 11.43 2.54) (size 2.032 2.032) (drill 1.143) |
600 |
(layers *.Cu *.Mask F.SilkS) |
|
601 |
(net 22 N-0000054) |
|
602 |
) |
|
603 |
(pad 2 thru_hole oval (at 11.43 0) (size 2.032 1.524) (drill 1.143) |
|
604 |
(layers *.Cu *.Mask F.SilkS) |
|
605 |
(net 20 N-0000050) |
|
606 |
) |
|
607 |
(pad 3 thru_hole oval (at 11.43 -2.54) (size 2.032 1.524) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
608 |
(layers *.Cu *.Mask F.SilkS) |
609 |
(net 2 /VCC) |
|
610 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
611 |
(pad 4 thru_hole oval (at 11.43 -5.08) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
612 |
(layers *.Cu *.Mask F.SilkS) |
613 |
(net 1 /GND) |
|
614 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
615 |
(pad 5 thru_hole circle (at -11.43 7.62) (size 2.032 2.032) (drill 1.143) |
616 |
(layers *.Cu *.Mask F.SilkS) |
|
617 |
) |
|
618 |
(pad 6 thru_hole circle (at -11.43 5.08) (size 2.032 2.032) (drill 1.143) |
|
619 |
(layers *.Cu *.Mask F.SilkS) |
|
620 |
) |
|
621 |
(pad 7 thru_hole circle (at -11.43 2.54) (size 2.032 2.032) (drill 1.143) |
|
622 |
(layers *.Cu *.Mask F.SilkS) |
|
623 |
) |
|
624 |
(pad 8 thru_hole circle (at -11.43 0) (size 2.032 2.032) (drill 1.143) |
|
625 |
(layers *.Cu *.Mask F.SilkS) |
|
626 |
) |
|
627 |
(pad 9 thru_hole circle (at -11.43 -2.54) (size 2.032 2.032) (drill 1.143) |
|
628 |
(layers *.Cu *.Mask F.SilkS) |
|
629 |
) |
|
630 |
(pad 10 thru_hole circle (at -11.43 -5.08) (size 2.032 2.032) (drill 1.143) |
|
631 |
(layers *.Cu *.Mask F.SilkS) |
|
632 |
) |
|
633 |
(pad 11 thru_hole circle (at -11.43 -7.62) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
634 |
(layers *.Cu *.Mask F.SilkS) |
635 |
) |
|
636 |
) |
|
637 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
638 |
(module Arduino_Mega_Shield_Partial (layer F.Cu) (tedit 534C83CF) (tstamp 534C656E) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
639 |
(at 49.53 77.47) |
640 |
(path /532A24F4) |
|
641 |
(fp_text reference U3 (at 0 -2.54) (layer F.SilkS) |
|
642 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
643 |
) |
|
644 |
(fp_text value ARDUINO_MEGA_SHIELD (at 0 0) (layer F.SilkS) |
|
645 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
646 |
) |
|
647 |
(fp_line (start 26.67 -31.75) (end 26.67 48.26) (layer F.SilkS) (width 0.15)) |
|
648 |
(fp_line (start -24.13 48.26) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
649 |
(fp_line (start 26.67 48.26) (end -24.13 48.26) (layer F.SilkS) (width 0.15)) |
|
650 |
(fp_line (start 26.67 -31.75) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
651 |
(pad 1 thru_hole circle (at -22.86 -11.43) (size 2.032 2.032) (drill 1.143) |
652 |
(layers *.Cu *.Mask F.SilkS) |
|
653 |
) |
|
654 |
(pad 2 thru_hole circle (at -22.86 -8.89) (size 2.032 2.032) (drill 1.143) |
|
655 |
(layers *.Cu *.Mask F.SilkS) |
|
656 |
) |
|
657 |
(pad 3 thru_hole oval (at -22.86 -6.35) (size 2.032 1.524) (drill 1.143) |
|
658 |
(layers *.Cu *.Mask F.SilkS) |
|
659 |
(net 25 N-0000080) |
|
660 |
) |
|
661 |
(pad 4 thru_hole oval (at -22.86 -3.81) (size 2.032 1.524) (drill 1.143) |
|
662 |
(layers *.Cu *.Mask F.SilkS) |
|
663 |
(net 1 /GND) |
|
664 |
) |
|
665 |
(pad 5 thru_hole circle (at -22.86 -1.27) (size 2.032 2.032) (drill 1.143) |
|
666 |
(layers *.Cu *.Mask F.SilkS) |
|
667 |
(net 1 /GND) |
|
668 |
) |
|
669 |
(pad 6 thru_hole circle (at -22.86 1.27) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
670 |
(layers *.Cu *.Mask F.SilkS) |
671 |
(net 2 /VCC) |
|
672 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
673 |
(pad 7 thru_hole circle (at -22.86 6.35) (size 2.032 2.032) (drill 1.143) |
674 |
(layers *.Cu *.Mask F.SilkS) |
|
675 |
(net 24 N-0000079) |
|
676 |
) |
|
677 |
(pad 8 thru_hole circle (at -22.86 8.89) (size 2.032 2.032) (drill 1.143) |
|
678 |
(layers *.Cu *.Mask F.SilkS) |
|
679 |
) |
|
680 |
(pad 9 thru_hole circle (at -22.86 11.43) (size 2.032 2.032) (drill 1.143) |
|
681 |
(layers *.Cu *.Mask F.SilkS) |
|
682 |
) |
|
683 |
(pad 10 thru_hole circle (at -22.86 13.97) (size 2.032 2.032) (drill 1.143) |
|
684 |
(layers *.Cu *.Mask F.SilkS) |
|
685 |
) |
|
686 |
(pad 11 thru_hole circle (at -22.86 16.51) (size 2.032 2.032) (drill 1.143) |
|
687 |
(layers *.Cu *.Mask F.SilkS) |
|
688 |
) |
|
689 |
(pad 12 thru_hole circle (at -22.86 19.05) (size 2.032 2.032) (drill 1.143) |
|
690 |
(layers *.Cu *.Mask F.SilkS) |
|
691 |
) |
|
692 |
(pad 13 thru_hole circle (at -22.86 21.59) (size 2.032 2.032) (drill 1.143) |
|
693 |
(layers *.Cu *.Mask F.SilkS) |
|
694 |
) |
|
695 |
(pad 14 thru_hole circle (at -22.86 24.13) (size 2.032 2.032) (drill 1.143) |
|
696 |
(layers *.Cu *.Mask F.SilkS) |
|
697 |
) |
|
698 |
(pad 15 thru_hole circle (at -22.86 29.21) (size 2.032 2.032) (drill 1.143) |
|
699 |
(layers *.Cu *.Mask F.SilkS) |
|
700 |
) |
|
701 |
(pad 16 thru_hole circle (at -22.86 31.75) (size 2.032 2.032) (drill 1.143) |
|
702 |
(layers *.Cu *.Mask F.SilkS) |
|
703 |
) |
|
704 |
(pad 17 thru_hole circle (at -22.86 34.29) (size 2.032 2.032) (drill 1.143) |
|
705 |
(layers *.Cu *.Mask F.SilkS) |
|
706 |
) |
|
707 |
(pad 18 thru_hole circle (at -22.86 36.83) (size 2.032 2.032) (drill 1.143) |
|
708 |
(layers *.Cu *.Mask F.SilkS) |
|
709 |
) |
|
710 |
(pad 19 thru_hole circle (at -22.86 39.37) (size 2.032 2.032) (drill 1.143) |
|
711 |
(layers *.Cu *.Mask F.SilkS) |
|
712 |
) |
|
713 |
(pad 20 thru_hole circle (at -22.86 41.91) (size 2.032 2.032) (drill 1.143) |
|
714 |
(layers *.Cu *.Mask F.SilkS) |
|
715 |
) |
|
716 |
(pad 21 thru_hole circle (at -22.86 44.45) (size 2.032 2.032) (drill 1.143) |
|
717 |
(layers *.Cu *.Mask F.SilkS) |
|
718 |
) |
|
719 |
(pad 23 thru_hole circle (at 25.4 41.91) (size 2.032 2.032) (drill 1.143) |
|
720 |
(layers *.Cu *.Mask F.SilkS) |
|
721 |
(net 22 N-0000054) |
|
722 |
) |
|
723 |
(pad 24 thru_hole circle (at 25.4 39.37) (size 2.032 2.032) (drill 1.143) |
|
724 |
(layers *.Cu *.Mask F.SilkS) |
|
725 |
(net 20 N-0000050) |
|
726 |
) |
|
727 |
(pad 25 thru_hole circle (at 25.4 36.83) (size 2.032 2.032) (drill 1.143) |
|
728 |
(layers *.Cu *.Mask F.SilkS) |
|
729 |
(net 16 N-0000034) |
|
730 |
) |
|
731 |
(pad 26 thru_hole circle (at 25.4 34.29) (size 2.032 2.032) (drill 1.143) |
|
732 |
(layers *.Cu *.Mask F.SilkS) |
|
733 |
(net 19 N-000005) |
|
734 |
) |
|
735 |
(pad 27 thru_hole circle (at 25.4 31.75) (size 2.032 2.032) (drill 1.143) |
|
736 |
(layers *.Cu *.Mask F.SilkS) |
|
737 |
) |
|
738 |
(pad 28 thru_hole circle (at 25.4 29.21) (size 2.032 2.032) (drill 1.143) |
|
739 |
(layers *.Cu *.Mask F.SilkS) |
|
740 |
) |
|
741 |
(pad 29 thru_hole circle (at 25.4 26.67) (size 2.032 2.032) (drill 1.143) |
|
742 |
(layers *.Cu *.Mask F.SilkS) |
|
743 |
) |
|
744 |
(pad 30 thru_hole circle (at 25.4 24.13) (size 2.032 2.032) (drill 1.143) |
|
745 |
(layers *.Cu *.Mask F.SilkS) |
|
746 |
) |
|
747 |
(pad 31 thru_hole circle (at 25.4 19.05) (size 2.032 2.032) (drill 1.143) |
|
748 |
(layers *.Cu *.Mask F.SilkS) |
|
749 |
) |
|
750 |
(pad 32 thru_hole circle (at 25.4 16.51) (size 2.032 2.032) (drill 1.143) |
|
751 |
(layers *.Cu *.Mask F.SilkS) |
|
752 |
) |
|
753 |
(pad 33 thru_hole circle (at 25.4 13.97) (size 2.032 2.032) (drill 1.143) |
|
754 |
(layers *.Cu *.Mask F.SilkS) |
|
755 |
) |
|
756 |
(pad 34 thru_hole circle (at 25.4 11.43) (size 2.032 2.032) (drill 1.143) |
|
757 |
(layers *.Cu *.Mask F.SilkS) |
|
758 |
) |
|
759 |
(pad 35 thru_hole circle (at 25.4 8.89) (size 2.032 2.032) (drill 1.143) |
|
760 |
(layers *.Cu *.Mask F.SilkS) |
|
761 |
) |
|
762 |
(pad 36 thru_hole circle (at 25.4 6.35) (size 2.032 2.032) (drill 1.143) |
|
763 |
(layers *.Cu *.Mask F.SilkS) |
|
764 |
) |
|
765 |
(pad 37 thru_hole circle (at 25.4 3.81) (size 2.032 2.032) (drill 1.143) |
|
766 |
(layers *.Cu *.Mask F.SilkS) |
|
767 |
) |
|
768 |
(pad 38 thru_hole circle (at 25.4 1.27) (size 2.032 2.032) (drill 1.143) |
|
769 |
(layers *.Cu *.Mask F.SilkS) |
|
770 |
) |
|
771 |
(pad 39 thru_hole circle (at 25.4 -2.54) (size 2.032 2.032) (drill 1.143) |
|
772 |
(layers *.Cu *.Mask F.SilkS) |
|
773 |
) |
|
774 |
(pad 40 thru_hole circle (at 25.4 -5.08) (size 2.032 2.032) (drill 1.143) |
|
775 |
(layers *.Cu *.Mask F.SilkS) |
|
776 |
) |
|
777 |
(pad 41 thru_hole circle (at 25.4 -7.62) (size 2.032 2.032) (drill 1.143) |
|
778 |
(layers *.Cu *.Mask F.SilkS) |
|
779 |
) |
|
780 |
(pad 42 thru_hole circle (at 25.4 -10.16) (size 2.032 2.032) (drill 1.143) |
|
781 |
(layers *.Cu *.Mask F.SilkS) |
|
782 |
) |
|
783 |
(pad 43 thru_hole circle (at 25.4 -12.7) (size 2.032 2.032) (drill 1.143) |
|
784 |
(layers *.Cu *.Mask F.SilkS) |
|
785 |
(net 21 N-0000052) |
|
786 |
) |
|
787 |
(pad 44 thru_hole circle (at 25.4 -15.24) (size 2.032 2.032) (drill 1.143) |
|
788 |
(layers *.Cu *.Mask F.SilkS) |
|
789 |
(net 18 N-0000048) |
|
790 |
) |
|
791 |
(pad 45 thru_hole circle (at 25.4 -17.78) (size 2.032 2.032) (drill 1.143) |
|
792 |
(layers *.Cu *.Mask F.SilkS) |
|
793 |
(net 1 /GND) |
|
794 |
) |
|
795 |
(pad 46 thru_hole circle (at 25.4 -20.32) (size 2.032 2.032) (drill 1.143) |
|
796 |
(layers *.Cu *.Mask F.SilkS) |
|
797 |
(net 25 N-0000080) |
|
798 |
) |
|
799 |
(pad 22 thru_hole circle (at -22.86 46.99) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
800 |
(layers *.Cu *.Mask F.SilkS) |
801 |
) |
|
802 |
) |
|
803 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
804 |
(module R3 (layer F.Cu) (tedit 534C928E) (tstamp 534C80B7) |
805 |
(at 46.99 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
806 |
(descr "Resitance 3 pas") |
807 |
(tags R) |
|
808 |
(path /53496D70) |
|
809 |
(autoplace_cost180 10) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
810 |
(fp_text reference R3 (at 0 0.127 90) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
811 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
812 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
813 |
(fp_text value 10k (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
814 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
815 |
) |
|
816 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
817 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
818 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
819 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
820 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
821 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
822 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
823 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
824 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
825 |
(layers *.Cu *.Mask F.SilkS) |
826 |
(net 1 /GND) |
|
827 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
828 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
829 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
830 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
831 |
) |
832 |
(model discret/resistor.wrl |
|
833 |
(at (xyz 0 0 0)) |
|
834 |
(scale (xyz 0.3 0.3 0.3)) |
|
835 |
(rotate (xyz 0 0 0)) |
|
836 |
) |
|
837 |
) |
|
838 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
839 |
(module R3 (layer F.Cu) (tedit 534C9292) (tstamp 5349AFE9) |
840 |
(at 44.45 71.12 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
841 |
(descr "Resitance 3 pas") |
842 |
(tags R) |
|
843 |
(path /53496D82) |
|
844 |
(autoplace_cost180 10) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
845 |
(fp_text reference R4 (at 0 0.127 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
846 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
847 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
848 |
(fp_text value 10k (at 0 0.127 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
849 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
850 |
) |
|
851 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
852 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
853 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
854 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
855 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
856 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
857 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
858 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
859 |
(pad 1 thru_hole circle (at -3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
860 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
861 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
862 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
863 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
864 |
(layers *.Cu *.Mask F.SilkS) |
865 |
(net 1 /GND) |
|
866 |
) |
|
867 |
(model discret/resistor.wrl |
|
868 |
(at (xyz 0 0 0)) |
|
869 |
(scale (xyz 0.3 0.3 0.3)) |
|
870 |
(rotate (xyz 0 0 0)) |
|
871 |
) |
|
872 |
) |
|
873 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
874 |
(module pin_array_4x2 (layer F.Cu) (tedit 534C8BAF) (tstamp 534C8C00) |
875 |
(at 66.04 92.71 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
876 |
(descr "Double rangee de contacts 2 x 4 pins") |
877 |
(tags CONN) |
|
878 |
(path /53496DB9) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
879 |
(fp_text reference P18 (at 0 -3.81 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
880 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
881 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
882 |
(fp_text value "ESC P & G" (at 0 3.81 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
883 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
884 |
) |
|
885 |
(fp_line (start -5.08 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
886 |
(fp_line (start 5.08 -2.54) (end 5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
887 |
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
888 |
(fp_line (start -5.08 2.54) (end -5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
889 |
(pad 1 thru_hole circle (at -3.81 1.27 270) (size 2.032 2.032) (drill 1.143) |
890 |
(layers *.Cu *.Mask F.SilkS) |
|
891 |
(net 2 /VCC) |
|
892 |
) |
|
893 |
(pad 2 thru_hole oval (at -3.81 -1.27 270) (size 2.032 1.524) (drill 1.143) |
|
894 |
(layers *.Cu *.Mask F.SilkS) |
|
895 |
(net 1 /GND) |
|
896 |
) |
|
897 |
(pad 3 thru_hole circle (at -1.27 1.27 270) (size 2.032 2.032) (drill 1.143) |
|
898 |
(layers *.Cu *.Mask F.SilkS) |
|
899 |
(net 2 /VCC) |
|
900 |
) |
|
901 |
(pad 4 thru_hole oval (at -1.27 -1.27 270) (size 2.032 1.524) (drill 1.143) |
|
902 |
(layers *.Cu *.Mask F.SilkS) |
|
903 |
(net 1 /GND) |
|
904 |
) |
|
905 |
(pad 5 thru_hole circle (at 1.27 1.27 270) (size 2.032 2.032) (drill 1.143) |
|
906 |
(layers *.Cu *.Mask F.SilkS) |
|
907 |
(net 2 /VCC) |
|
908 |
) |
|
909 |
(pad 6 thru_hole oval (at 1.27 -1.27 270) (size 2.032 1.524) (drill 1.143) |
|
910 |
(layers *.Cu *.Mask F.SilkS) |
|
911 |
(net 1 /GND) |
|
912 |
) |
|
913 |
(pad 7 thru_hole circle (at 3.81 1.27 270) (size 2.032 2.032) (drill 1.143) |
|
914 |
(layers *.Cu *.Mask F.SilkS) |
|
915 |
(net 2 /VCC) |
|
916 |
) |
|
917 |
(pad 8 thru_hole oval (at 3.81 -1.27 270) (size 2.032 1.524) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
918 |
(layers *.Cu *.Mask F.SilkS) |
919 |
(net 1 /GND) |
|
920 |
) |
|
921 |
(model pin_array/pins_array_4x2.wrl |
|
922 |
(at (xyz 0 0 0)) |
|
923 |
(scale (xyz 1 1 1)) |
|
924 |
(rotate (xyz 0 0 0)) |
|
925 |
) |
|
926 |
) |
|
927 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
928 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534C77CC) (tstamp 5349B010) |
929 |
(at 62.23 92.71 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
930 |
(descr "Double rangee de contacts 2 x 5 pins") |
931 |
(tags CONN) |
|
932 |
(path /53496DBF) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
933 |
(fp_text reference P17 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
934 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
935 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
936 |
(fp_text value "ESC Sig" (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
937 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
938 |
) |
|
939 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
940 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
941 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
942 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
943 |
(pad 1 thru_hole circle (at -3.81 0 270) (size 2.032 2.032) (drill 1.143) |
944 |
(layers *.Cu *.Mask F.SilkS) |
|
945 |
(net 17 N-000004) |
|
946 |
) |
|
947 |
(pad 2 thru_hole circle (at -1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
948 |
(layers *.Cu *.Mask F.SilkS) |
|
949 |
(net 15 N-000003) |
|
950 |
) |
|
951 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
952 |
(layers *.Cu *.Mask F.SilkS) |
|
953 |
(net 7 N-000002) |
|
954 |
) |
|
955 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
956 |
(layers *.Cu *.Mask F.SilkS) |
957 |
(net 3 N-000001) |
|
958 |
) |
|
959 |
(model pin_array\pins_array_4x1.wrl |
|
960 |
(at (xyz 0 0 0)) |
|
961 |
(scale (xyz 1 1 1)) |
|
962 |
(rotate (xyz 0 0 0)) |
|
963 |
) |
|
964 |
) |
|
965 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
966 |
(module D3 (layer F.Cu) (tedit 534C9179) (tstamp 5349B02C) |
967 |
(at 34.29 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
968 |
(descr "Diode 3 pas") |
969 |
(tags "DIODE DEV") |
|
970 |
(path /53496D88) |
|
971 |
(fp_text reference D1 (at 0 0 90) (layer F.SilkS) |
|
972 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
973 |
) |
|
974 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
975 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
976 |
) |
|
977 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
978 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
979 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
980 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
981 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
982 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
983 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
984 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
985 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
986 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
987 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
988 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
989 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
990 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
991 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
992 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
993 |
(net 14 N-0000026) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
994 |
) |
995 |
(model discret/diode.wrl |
|
996 |
(at (xyz 0 0 0)) |
|
997 |
(scale (xyz 0.3 0.3 0.3)) |
|
998 |
(rotate (xyz 0 0 0)) |
|
999 |
) |
|
1000 |
) |
|
1001 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1002 |
(module D3 (layer F.Cu) (tedit 534C918B) (tstamp 5349B03C) |
1003 |
(at 41.91 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1004 |
(descr "Diode 3 pas") |
1005 |
(tags "DIODE DEV") |
|
1006 |
(path /53496D8E) |
|
1007 |
(fp_text reference D4 (at 0 0 90) (layer F.SilkS) |
|
1008 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1009 |
) |
|
1010 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1011 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1012 |
) |
|
1013 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1014 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1015 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1016 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1017 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1018 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1019 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1020 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1021 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1022 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1023 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1024 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1025 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1026 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1027 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1028 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1029 |
(net 13 N-0000025) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1030 |
) |
1031 |
(model discret/diode.wrl |
|
1032 |
(at (xyz 0 0 0)) |
|
1033 |
(scale (xyz 0.3 0.3 0.3)) |
|
1034 |
(rotate (xyz 0 0 0)) |
|
1035 |
) |
|
1036 |
) |
|
1037 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1038 |
(module D3 (layer F.Cu) (tedit 534C9180) (tstamp 5349B04C) |
1039 |
(at 36.83 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1040 |
(descr "Diode 3 pas") |
1041 |
(tags "DIODE DEV") |
|
1042 |
(path /53496D94) |
|
1043 |
(fp_text reference D2 (at 0 0 90) (layer F.SilkS) |
|
1044 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1045 |
) |
|
1046 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1047 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1048 |
) |
|
1049 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1050 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1051 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1052 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1053 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1054 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1055 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1056 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1057 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1058 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1059 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1060 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1061 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1062 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1063 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1064 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1065 |
(net 11 N-0000023) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1066 |
) |
1067 |
(model discret/diode.wrl |
|
1068 |
(at (xyz 0 0 0)) |
|
1069 |
(scale (xyz 0.3 0.3 0.3)) |
|
1070 |
(rotate (xyz 0 0 0)) |
|
1071 |
) |
|
1072 |
) |
|
1073 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1074 |
(module D3 (layer F.Cu) (tedit 534C9186) (tstamp 5349B05C) |
1075 |
(at 39.37 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1076 |
(descr "Diode 3 pas") |
1077 |
(tags "DIODE DEV") |
|
1078 |
(path /53496D9A) |
|
1079 |
(fp_text reference D3 (at 0 0 90) (layer F.SilkS) |
|
1080 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1081 |
) |
|
1082 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1083 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1084 |
) |
|
1085 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1086 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1087 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1088 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1089 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1090 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1091 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1092 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1093 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1094 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1095 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1096 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1097 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1098 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1099 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1100 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1101 |
(net 10 N-0000022) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1102 |
) |
1103 |
(model discret/diode.wrl |
|
1104 |
(at (xyz 0 0 0)) |
|
1105 |
(scale (xyz 0.3 0.3 0.3)) |
|
1106 |
(rotate (xyz 0 0 0)) |
|
1107 |
) |
|
1108 |
) |
|
1109 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1110 |
(module D3 (layer F.Cu) (tedit 534C973E) (tstamp 5349B06C) |
1111 |
(at 53.34 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1112 |
(descr "Diode 3 pas") |
1113 |
(tags "DIODE DEV") |
|
1114 |
(path /53496DA0) |
|
1115 |
(fp_text reference D5 (at 0 0 90) (layer F.SilkS) |
|
1116 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1117 |
) |
|
1118 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1119 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1120 |
) |
|
1121 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1122 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1123 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1124 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1125 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1126 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1127 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1128 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1129 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1130 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1131 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1132 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1133 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1134 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1135 |
(pad 1 thru_hole oval (at -3.81 0 90) (size 2.032 1.524) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1136 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1137 |
(net 9 N-0000021) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1138 |
) |
1139 |
(model discret/diode.wrl |
|
1140 |
(at (xyz 0 0 0)) |
|
1141 |
(scale (xyz 0.3 0.3 0.3)) |
|
1142 |
(rotate (xyz 0 0 0)) |
|
1143 |
) |
|
1144 |
) |
|
1145 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1146 |
(module D3 (layer F.Cu) (tedit 534C9281) (tstamp 5349B07C) |
1147 |
(at 55.88 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1148 |
(descr "Diode 3 pas") |
1149 |
(tags "DIODE DEV") |
|
1150 |
(path /53496DA6) |
|
1151 |
(fp_text reference D6 (at 0 0 90) (layer F.SilkS) |
|
1152 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1153 |
) |
|
1154 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1155 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1156 |
) |
|
1157 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1158 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1159 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1160 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1161 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1162 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1163 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1164 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1165 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1166 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1167 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1168 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1169 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1170 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1171 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1172 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1173 |
(net 8 N-0000020) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1174 |
) |
1175 |
(model discret/diode.wrl |
|
1176 |
(at (xyz 0 0 0)) |
|
1177 |
(scale (xyz 0.3 0.3 0.3)) |
|
1178 |
(rotate (xyz 0 0 0)) |
|
1179 |
) |
|
1180 |
) |
|
1181 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1182 |
(module D3 (layer F.Cu) (tedit 534C927B) (tstamp 5349B08C) |
1183 |
(at 58.42 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1184 |
(descr "Diode 3 pas") |
1185 |
(tags "DIODE DEV") |
|
1186 |
(path /53496DAC) |
|
1187 |
(fp_text reference D7 (at 0 0 90) (layer F.SilkS) |
|
1188 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1189 |
) |
|
1190 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1191 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1192 |
) |
|
1193 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1194 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1195 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1196 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1197 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1198 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1199 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1200 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1201 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1202 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1203 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1204 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1205 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1206 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1207 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1208 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1209 |
(net 6 N-0000019) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1210 |
) |
1211 |
(model discret/diode.wrl |
|
1212 |
(at (xyz 0 0 0)) |
|
1213 |
(scale (xyz 0.3 0.3 0.3)) |
|
1214 |
(rotate (xyz 0 0 0)) |
|
1215 |
) |
|
1216 |
) |
|
1217 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1218 |
(module D3 (layer F.Cu) (tedit 534C9274) (tstamp 5349B09C) |
1219 |
(at 60.96 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1220 |
(descr "Diode 3 pas") |
1221 |
(tags "DIODE DEV") |
|
1222 |
(path /53496DB2) |
|
1223 |
(fp_text reference D8 (at 0 0 90) (layer F.SilkS) |
|
1224 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1225 |
) |
|
1226 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1227 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1228 |
) |
|
1229 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1230 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1231 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1232 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1233 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1234 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1235 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1236 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1237 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1238 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1239 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1240 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1241 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1242 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1243 |
(pad 1 thru_hole oval (at -3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1244 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1245 |
(net 5 N-0000018) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1246 |
) |
1247 |
(model discret/diode.wrl |
|
1248 |
(at (xyz 0 0 0)) |
|
1249 |
(scale (xyz 0.3 0.3 0.3)) |
|
1250 |
(rotate (xyz 0 0 0)) |
|
1251 |
) |
|
1252 |
) |
|
1253 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1254 |
(module Arduino_Mini_Pro_Mount (layer F.Cu) (tedit 534C9713) (tstamp 534C97E9) |
1255 |
(at 49.53 71.12 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1256 |
(path /53497285) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1257 |
(fp_text reference U4 (at -1.27 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1258 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1259 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1260 |
(fp_text value ARDUINO_MINI_PRO_MOUNT (at 1.27 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1261 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1262 |
) |
|
1263 |
(fp_line (start -10.16 15.24) (end 7.62 15.24) (layer F.SilkS) (width 0.15)) |
|
1264 |
(fp_line (start 7.62 15.24) (end 7.62 -17.78) (layer F.SilkS) (width 0.15)) |
|
1265 |
(fp_line (start 7.62 -17.78) (end -10.16 -17.78) (layer F.SilkS) (width 0.15)) |
|
1266 |
(fp_line (start -10.16 -17.78) (end -10.16 15.24) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1267 |
(pad 1 thru_hole oval (at -8.89 -13.97 90) (size 2.032 1.524) (drill 1.143) |
1268 |
(layers *.Cu *.Mask F.SilkS) |
|
1269 |
(net 16 N-0000034) |
|
1270 |
) |
|
1271 |
(pad 2 thru_hole oval (at -8.89 -11.43 90) (size 2.032 1.524) (drill 1.143) |
|
1272 |
(layers *.Cu *.Mask F.SilkS) |
|
1273 |
(net 19 N-000005) |
|
1274 |
) |
|
1275 |
(pad 3 thru_hole oval (at -8.89 -8.89 90) (size 2.032 1.524) (drill 1.143) |
|
1276 |
(layers *.Cu *.Mask F.SilkS) |
|
1277 |
) |
|
1278 |
(pad 4 thru_hole oval (at -8.89 -6.35 90) (size 2.032 1.524) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1279 |
(layers *.Cu *.Mask F.SilkS) |
1280 |
(net 1 /GND) |
|
1281 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1282 |
(pad 5 thru_hole circle (at -8.89 -3.81 90) (size 2.032 2.032) (drill 1.143) |
1283 |
(layers *.Cu *.Mask F.SilkS) |
|
1284 |
(net 12 N-0000024) |
|
1285 |
) |
|
1286 |
(pad 6 thru_hole oval (at -8.89 -1.27 90) (size 2.032 1.524) (drill 1.143) |
|
1287 |
(layers *.Cu *.Mask F.SilkS) |
|
1288 |
(net 4 N-0000017) |
|
1289 |
) |
|
1290 |
(pad 7 thru_hole oval (at -8.89 1.27 90) (size 2.032 1.524) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1291 |
(layers *.Cu *.Mask F.SilkS) |
1292 |
(net 3 N-000001) |
|
1293 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1294 |
(pad 8 thru_hole circle (at -8.89 3.81 90) (size 2.032 2.032) (drill 1.143) |
1295 |
(layers *.Cu *.Mask F.SilkS) |
|
1296 |
(net 7 N-000002) |
|
1297 |
) |
|
1298 |
(pad 9 thru_hole oval (at -8.89 6.35 90) (size 1.524 2.032) (drill 1.143) |
|
1299 |
(layers *.Cu *.Mask F.SilkS) |
|
1300 |
(net 15 N-000003) |
|
1301 |
) |
|
1302 |
(pad 10 thru_hole oval (at -8.89 8.89 90) (size 1.524 2.032) (drill 1.143) |
|
1303 |
(layers *.Cu *.Mask F.SilkS) |
|
1304 |
(net 17 N-000004) |
|
1305 |
) |
|
1306 |
(pad 11 thru_hole oval (at -8.89 11.43 90) (size 1.524 2.032) (drill 1.143) |
|
1307 |
(layers *.Cu *.Mask F.SilkS) |
|
1308 |
) |
|
1309 |
(pad 12 thru_hole oval (at -8.89 13.97 90) (size 1.524 2.032) (drill 1.143) |
|
1310 |
(layers *.Cu *.Mask F.SilkS) |
|
1311 |
) |
|
1312 |
(pad 13 thru_hole circle (at 6.35 13.97 90) (size 2.032 2.032) (drill 1.143) |
|
1313 |
(layers *.Cu *.Mask F.SilkS) |
|
1314 |
) |
|
1315 |
(pad 14 thru_hole circle (at 6.35 11.43 90) (size 2.032 2.032) (drill 1.143) |
|
1316 |
(layers *.Cu *.Mask F.SilkS) |
|
1317 |
) |
|
1318 |
(pad 15 thru_hole circle (at 6.35 8.89 90) (size 2.032 2.032) (drill 1.143) |
|
1319 |
(layers *.Cu *.Mask F.SilkS) |
|
1320 |
) |
|
1321 |
(pad 16 thru_hole circle (at 6.35 6.35 90) (size 2.032 2.032) (drill 1.143) |
|
1322 |
(layers *.Cu *.Mask F.SilkS) |
|
1323 |
) |
|
1324 |
(pad 17 thru_hole circle (at 6.35 3.81 90) (size 2.032 2.032) (drill 1.143) |
|
1325 |
(layers *.Cu *.Mask F.SilkS) |
|
1326 |
) |
|
1327 |
(pad 18 thru_hole circle (at 6.35 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
1328 |
(layers *.Cu *.Mask F.SilkS) |
|
1329 |
) |
|
1330 |
(pad 19 thru_hole circle (at 6.35 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
1331 |
(layers *.Cu *.Mask F.SilkS) |
|
1332 |
) |
|
1333 |
(pad 20 thru_hole circle (at 6.35 -3.81 90) (size 2.032 2.032) (drill 1.143) |
|
1334 |
(layers *.Cu *.Mask F.SilkS) |
|
1335 |
) |
|
1336 |
(pad 21 thru_hole circle (at 6.35 -6.35 90) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1337 |
(layers *.Cu *.Mask F.SilkS) |
1338 |
(net 2 /VCC) |
|
1339 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1340 |
(pad 22 thru_hole oval (at 6.35 -8.89 90) (size 1.524 2.032) (drill 1.143) |
1341 |
(layers *.Cu *.Mask F.SilkS) |
|
1342 |
) |
|
1343 |
(pad 23 thru_hole oval (at 6.35 -11.43 90) (size 1.524 2.032) (drill 1.143) |
|
1344 |
(layers *.Cu *.Mask F.SilkS) |
|
1345 |
(net 1 /GND) |
|
1346 |
) |
|
1347 |
(pad 24 thru_hole oval (at 6.35 -13.97 90) (size 1.524 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1348 |
(layers *.Cu *.Mask F.SilkS) |
1349 |
) |
|
1350 |
) |
|
1351 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1352 |
(module 9x3_Conn_Block (layer F.Cu) (tedit 534C7723) (tstamp 534C9726) |
1353 |
(at 57.15 116.84 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1354 |
(path /53497B7A) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1355 |
(fp_text reference U5 (at -5.08 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1356 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1357 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1358 |
(fp_text value 9X3_CONN_BLOCK (at 5.08 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1359 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
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1364 |
(fp_line (start -3.81 11.43) (end -3.81 -11.43) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1365 |
(pad 1 thru_hole circle (at -2.54 -10.16 90) (size 2.032 2.032) (drill 1.143) |
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1451 |
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1453 |
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1454 |
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1455 |
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1456 |
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1458 |
(layers *.Cu *.Mask F.SilkS) |
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1459 |
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1461 |
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1463 |
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1466 |
(layers *.Cu *.Mask F.SilkS) |
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1467 |
(net 5 N-0000018) |
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1469 |
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1470 |
(layers *.Cu *.Mask F.SilkS) |
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|
1473 |
||
1474 |
(module LM78XXV (layer F.Cu) (tedit 534C7888) (tstamp 5345C7C5) |
|
1475 |
(at 36.83 114.3 90) |
|
1476 |
(descr "Regulateur TO220 serie LM78xx") |
|
1477 |
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(layers *.Cu *.Mask F.SilkS) |
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1494 |
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|
1495 |
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|
1496 |
(pad GND thru_hole circle (at 0 0 90) (size 2.032 2.032) (drill 1.143) |
|
1497 |
(layers *.Cu *.Mask F.SilkS) |
|
1498 |
(net 1 /GND) |
|
1499 |
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|
1500 |
(pad VO thru_hole circle (at 0 2.54 90) (size 2.032 2.032) (drill 1.143) |
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1501 |
(layers *.Cu *.Mask F.SilkS) |
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1502 |
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|
1505 |
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1506 |
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1507 |
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1510 |
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1511 |
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1513 |
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1514 |
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1532 |
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1533 |
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|
1723 |
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|
1724 |
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|
1725 |
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|
1726 |
(segment (start 24.13 73.66) (end 25.4 72.39) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8454)) |
|
1727 |
(segment (start 24.13 102.87) (end 24.13 73.66) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8453)) |
|
1728 |
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|
1729 |
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|
1730 |
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|
1731 |
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|
1732 |
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|
1733 |
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|
1734 |
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|
1735 |
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|
1736 |
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|
1737 |
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|
1738 |
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|
1739 |
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|
1740 |
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|
1741 |
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|
1742 |
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|
1743 |
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|
1744 |
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|
1745 |
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|
1746 |
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|
1747 |
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|
1748 |
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|
1749 |
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|
1750 |
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|
1751 |
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|
1752 |
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|
1753 |
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|
1754 |
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|
1755 |
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|
1756 |
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|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1757 |
|
1758 |
) |