bzr branch
http://bzr.ed.am/elec/quadcopter
|
50
by dan
finnished connecting all of the components together #=O) |
1 |
(kicad_pcb (version 3) (host pcbnew "(2013-jul-07)-stable") |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
2 |
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3 |
(general |
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|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
4 |
(links 98) |
|
50
by dan
finnished connecting all of the components together #=O) |
5 |
(no_connects 0) |
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
6 |
(area 23.9395 45.390999 77.660501 126.059001) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
7 |
(thickness 1.6) |
8 |
(drawings 0) |
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|
50
by dan
finnished connecting all of the components together #=O) |
9 |
(tracks 261) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
10 |
(zones 0) |
11 |
(modules 33) |
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12 |
(nets 26) |
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13 |
) |
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14 |
||
15 |
(page A3) |
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16 |
(layers |
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17 |
(15 F.Cu signal) |
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18 |
(0 B.Cu signal) |
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19 |
(16 B.Adhes user) |
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20 |
(17 F.Adhes user) |
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21 |
(18 B.Paste user) |
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22 |
(19 F.Paste user) |
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23 |
(20 B.SilkS user) |
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24 |
(21 F.SilkS user) |
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25 |
(22 B.Mask user) |
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26 |
(23 F.Mask user) |
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27 |
(24 Dwgs.User user) |
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28 |
(25 Cmts.User user) |
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29 |
(26 Eco1.User user) |
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30 |
(27 Eco2.User user) |
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31 |
(28 Edge.Cuts user) |
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32 |
) |
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33 |
||
34 |
(setup |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
35 |
(last_trace_width 0.381) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
36 |
(trace_clearance 0.254) |
37 |
(zone_clearance 0.508) |
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38 |
(zone_45_only no) |
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39 |
(trace_min 0.254) |
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40 |
(segment_width 0.2) |
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41 |
(edge_width 0.15) |
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42 |
(via_size 0.889) |
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43 |
(via_drill 0.635) |
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44 |
(via_min_size 0.889) |
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45 |
(via_min_drill 0.508) |
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46 |
(uvia_size 0.508) |
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47 |
(uvia_drill 0.127) |
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48 |
(uvias_allowed no) |
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49 |
(uvia_min_size 0.508) |
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50 |
(uvia_min_drill 0.127) |
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51 |
(pcb_text_width 0.3) |
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52 |
(pcb_text_size 1.5 1.5) |
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53 |
(mod_edge_width 0.15) |
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54 |
(mod_text_size 1.5 1.5) |
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55 |
(mod_text_width 0.15) |
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|
50
by dan
finnished connecting all of the components together #=O) |
56 |
(pad_size 1.524 2.032) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
57 |
(pad_drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
58 |
(pad_to_mask_clearance 0.2) |
59 |
(aux_axis_origin 0 0) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
60 |
(visible_elements FFFE3FBF) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
61 |
(pcbplotparams |
62 |
(layerselection 3178497) |
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63 |
(usegerberextensions true) |
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64 |
(excludeedgelayer true) |
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65 |
(linewidth 0.100000) |
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66 |
(plotframeref false) |
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67 |
(viasonmask false) |
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68 |
(mode 1) |
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69 |
(useauxorigin false) |
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70 |
(hpglpennumber 1) |
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71 |
(hpglpenspeed 20) |
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72 |
(hpglpendiameter 15) |
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73 |
(hpglpenoverlay 2) |
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74 |
(psnegative false) |
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75 |
(psa4output false) |
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76 |
(plotreference true) |
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77 |
(plotvalue true) |
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78 |
(plotothertext true) |
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79 |
(plotinvisibletext false) |
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80 |
(padsonsilk false) |
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81 |
(subtractmaskfromsilk false) |
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82 |
(outputformat 1) |
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83 |
(mirror false) |
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84 |
(drillshape 1) |
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85 |
(scaleselection 1) |
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86 |
(outputdirectory "")) |
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87 |
) |
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88 |
||
89 |
(net 0 "") |
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90 |
(net 1 /GND) |
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91 |
(net 2 /VCC) |
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92 |
(net 3 N-000001) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
93 |
(net 4 N-0000017) |
94 |
(net 5 N-0000018) |
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95 |
(net 6 N-0000019) |
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96 |
(net 7 N-000002) |
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97 |
(net 8 N-0000020) |
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98 |
(net 9 N-0000021) |
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99 |
(net 10 N-0000022) |
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100 |
(net 11 N-0000023) |
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101 |
(net 12 N-0000024) |
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102 |
(net 13 N-0000025) |
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103 |
(net 14 N-0000026) |
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104 |
(net 15 N-000003) |
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105 |
(net 16 N-0000034) |
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106 |
(net 17 N-000004) |
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107 |
(net 18 N-0000048) |
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108 |
(net 19 N-000005) |
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109 |
(net 20 N-0000050) |
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110 |
(net 21 N-0000052) |
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111 |
(net 22 N-0000054) |
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112 |
(net 23 N-0000060) |
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113 |
(net 24 N-0000079) |
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114 |
(net 25 N-0000080) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
115 |
|
116 |
(net_class Default "This is the default net class." |
|
117 |
(clearance 0.254) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
118 |
(trace_width 0.381) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
119 |
(via_dia 0.889) |
120 |
(via_drill 0.635) |
|
121 |
(uvia_dia 0.508) |
|
122 |
(uvia_drill 0.127) |
|
123 |
(add_net "") |
|
124 |
(add_net /GND) |
|
125 |
(add_net /VCC) |
|
126 |
(add_net N-000001) |
|
127 |
(add_net N-0000017) |
|
128 |
(add_net N-0000018) |
|
129 |
(add_net N-0000019) |
|
130 |
(add_net N-000002) |
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|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
131 |
(add_net N-0000020) |
132 |
(add_net N-0000021) |
|
133 |
(add_net N-0000022) |
|
134 |
(add_net N-0000023) |
|
135 |
(add_net N-0000024) |
|
136 |
(add_net N-0000025) |
|
137 |
(add_net N-0000026) |
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|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
138 |
(add_net N-000003) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
139 |
(add_net N-0000034) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
140 |
(add_net N-000004) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
141 |
(add_net N-0000048) |
142 |
(add_net N-000005) |
|
143 |
(add_net N-0000050) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
144 |
(add_net N-0000052) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
145 |
(add_net N-0000054) |
146 |
(add_net N-0000060) |
|
147 |
(add_net N-0000079) |
|
148 |
(add_net N-0000080) |
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|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
149 |
) |
150 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
151 |
(module R3 (layer F.Cu) (tedit 534C7795) (tstamp 5345C6FF) |
|
50
by dan
finnished connecting all of the components together #=O) |
152 |
(at 34.29 106.68 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
153 |
(descr "Resitance 3 pas") |
154 |
(tags R) |
|
155 |
(path /5320CEF3) |
|
156 |
(autoplace_cost180 10) |
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|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
157 |
(fp_text reference R1 (at 0 0.127 90) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
158 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
159 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
160 |
(fp_text value 20K (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
161 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
162 |
) |
|
163 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
164 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
165 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
166 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
167 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
168 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
169 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
170 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
171 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
172 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
173 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
174 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
175 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
176 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
177 |
(net 24 N-0000079) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
178 |
) |
179 |
(model discret/resistor.wrl |
|
180 |
(at (xyz 0 0 0)) |
|
181 |
(scale (xyz 0.3 0.3 0.3)) |
|
182 |
(rotate (xyz 0 0 0)) |
|
183 |
) |
|
184 |
) |
|
185 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
186 |
(module R3 (layer F.Cu) (tedit 534C956E) (tstamp 5345CB8B) |
|
50
by dan
finnished connecting all of the components together #=O) |
187 |
(at 36.83 106.68 270) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
188 |
(descr "Resitance 3 pas") |
189 |
(tags R) |
|
190 |
(path /5320CF02) |
|
191 |
(autoplace_cost180 10) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
192 |
(fp_text reference R2 (at 0 0.127 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
193 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
194 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
195 |
(fp_text value 10K (at 0 0.127 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
196 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
197 |
) |
|
198 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
199 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
200 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
201 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
202 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
203 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
204 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
205 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
206 |
(pad 1 thru_hole circle (at -3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
207 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
208 |
(net 24 N-0000079) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
209 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
210 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
211 |
(layers *.Cu *.Mask F.SilkS) |
212 |
(net 1 /GND) |
|
213 |
) |
|
214 |
(model discret/resistor.wrl |
|
215 |
(at (xyz 0 0 0)) |
|
216 |
(scale (xyz 0.3 0.3 0.3)) |
|
217 |
(rotate (xyz 0 0 0)) |
|
218 |
) |
|
219 |
) |
|
220 |
||
221 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C718) |
|
222 |
(at 39.37 58.42 90) |
|
223 |
(path /5321281E) |
|
224 |
(attr virtual) |
|
225 |
(fp_text reference P5 (at -1.905 -3.81 90) (layer F.SilkS) |
|
226 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
227 |
) |
|
228 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
229 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
230 |
) |
|
231 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
232 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
233 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
234 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
235 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
236 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
237 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
238 |
(net 2 /VCC) |
|
239 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
240 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
241 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
242 |
(net 1 /GND) |
|
243 |
) |
|
244 |
) |
|
245 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
246 |
(module PINHEAD1-2 (layer F.Cu) (tedit 534C790C) (tstamp 534C7AD5) |
247 |
(at 35.56 119.38 180) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
248 |
(path /53212E1B) |
249 |
(attr virtual) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
250 |
(fp_text reference P1 (at -1.905 -3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
251 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
252 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
253 |
(fp_text value CONN_2 (at 0 3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
254 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
255 |
) |
|
256 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
257 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
258 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
259 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
260 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
261 |
(pad 1 thru_hole oval (at -1.27 0 180) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
262 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
263 |
(net 1 /GND) |
|
264 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
265 |
(pad 2 thru_hole oval (at 1.27 0 180) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
266 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
267 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
268 |
) |
269 |
) |
|
270 |
||
271 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C739) |
|
272 |
(at 69.85 58.42 90) |
|
273 |
(path /532128A9) |
|
274 |
(attr virtual) |
|
275 |
(fp_text reference P13 (at -1.905 -3.81 90) (layer F.SilkS) |
|
276 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
277 |
) |
|
278 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
279 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
280 |
) |
|
281 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
282 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
283 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
284 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
285 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
286 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
287 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
288 |
(net 2 /VCC) |
|
289 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
290 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
291 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
292 |
(net 1 /GND) |
|
293 |
) |
|
294 |
) |
|
295 |
||
296 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C744) |
|
297 |
(at 62.23 58.42 90) |
|
298 |
(path /5321289A) |
|
299 |
(attr virtual) |
|
300 |
(fp_text reference P11 (at -1.905 -3.81 90) (layer F.SilkS) |
|
301 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
302 |
) |
|
303 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
304 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
305 |
) |
|
306 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
307 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
308 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
309 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
310 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
311 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
312 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
313 |
(net 2 /VCC) |
|
314 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
315 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
316 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
317 |
(net 1 /GND) |
|
318 |
) |
|
319 |
) |
|
320 |
||
321 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C74F) |
|
322 |
(at 54.61 58.42 90) |
|
323 |
(path /5321288B) |
|
324 |
(attr virtual) |
|
325 |
(fp_text reference P9 (at -1.905 -3.81 90) (layer F.SilkS) |
|
326 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
327 |
) |
|
328 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
329 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
330 |
) |
|
331 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
332 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
333 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
334 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
335 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
336 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
337 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
338 |
(net 2 /VCC) |
|
339 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
340 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
341 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
342 |
(net 1 /GND) |
|
343 |
) |
|
344 |
) |
|
345 |
||
346 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C75A) |
|
347 |
(at 46.99 58.42 90) |
|
348 |
(path /5321287C) |
|
349 |
(attr virtual) |
|
350 |
(fp_text reference P7 (at -1.905 -3.81 90) (layer F.SilkS) |
|
351 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
352 |
) |
|
353 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
354 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
355 |
) |
|
356 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
357 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
358 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
359 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
360 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
361 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
362 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
363 |
(net 2 /VCC) |
|
364 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
365 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
366 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
367 |
(net 1 /GND) |
|
368 |
) |
|
369 |
) |
|
370 |
||
371 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C765) |
|
372 |
(at 31.75 58.42 90) |
|
373 |
(path /5321280F) |
|
374 |
(attr virtual) |
|
375 |
(fp_text reference P3 (at -1.905 -3.81 90) (layer F.SilkS) |
|
376 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
377 |
) |
|
378 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
379 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
380 |
) |
|
381 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
382 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
383 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
384 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
385 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
386 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
387 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
388 |
(net 2 /VCC) |
|
389 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
390 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
391 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
392 |
(net 1 /GND) |
|
393 |
) |
|
394 |
) |
|
395 |
||
396 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C770) |
|
397 |
(at 69.85 50.8 90) |
|
398 |
(path /53212800) |
|
399 |
(attr virtual) |
|
400 |
(fp_text reference P14 (at -1.905 -3.81 90) (layer F.SilkS) |
|
401 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
402 |
) |
|
403 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
404 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
405 |
) |
|
406 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
407 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
408 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
409 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
410 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
411 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
412 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
413 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
414 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
415 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
416 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
417 |
(net 1 /GND) |
|
418 |
) |
|
419 |
) |
|
420 |
||
421 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C77B) |
|
422 |
(at 62.23 50.8 90) |
|
423 |
(path /532127F1) |
|
424 |
(attr virtual) |
|
425 |
(fp_text reference P12 (at -1.905 -3.81 90) (layer F.SilkS) |
|
426 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
427 |
) |
|
428 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
429 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
430 |
) |
|
431 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
432 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
433 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
434 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
435 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
436 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
437 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
438 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
439 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
440 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
441 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
442 |
(net 1 /GND) |
|
443 |
) |
|
444 |
) |
|
445 |
||
446 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C786) |
|
447 |
(at 54.61 50.8 90) |
|
448 |
(path /532127E2) |
|
449 |
(attr virtual) |
|
450 |
(fp_text reference P10 (at -1.905 -3.81 90) (layer F.SilkS) |
|
451 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
452 |
) |
|
453 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
454 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
455 |
) |
|
456 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
457 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
458 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
459 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
460 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
461 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
462 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
463 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
464 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
465 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
466 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
467 |
(net 1 /GND) |
|
468 |
) |
|
469 |
) |
|
470 |
||
471 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C791) |
|
472 |
(at 46.99 50.8 90) |
|
473 |
(path /532127D3) |
|
474 |
(attr virtual) |
|
475 |
(fp_text reference P8 (at -1.905 -3.81 90) (layer F.SilkS) |
|
476 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
477 |
) |
|
478 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
479 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
480 |
) |
|
481 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
482 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
483 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
484 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
485 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
486 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
487 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
488 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
489 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
490 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
491 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
492 |
(net 1 /GND) |
|
493 |
) |
|
494 |
) |
|
495 |
||
496 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C79C) |
|
497 |
(at 39.37 50.8 90) |
|
498 |
(path /532127B5) |
|
499 |
(attr virtual) |
|
500 |
(fp_text reference P6 (at -1.905 -3.81 90) (layer F.SilkS) |
|
501 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
502 |
) |
|
503 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
504 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
505 |
) |
|
506 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
507 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
508 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
509 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
510 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
511 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
512 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
513 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
514 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
515 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
516 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
517 |
(net 1 /GND) |
|
518 |
) |
|
519 |
) |
|
520 |
||
521 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C7A7) |
|
522 |
(at 31.75 50.8 90) |
|
523 |
(path /53212777) |
|
524 |
(attr virtual) |
|
525 |
(fp_text reference P4 (at -1.905 -3.81 90) (layer F.SilkS) |
|
526 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
527 |
) |
|
528 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
529 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
530 |
) |
|
531 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
532 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
533 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
534 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
535 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
536 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
537 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
538 |
(net 23 N-0000060) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
539 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
540 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
541 |
(layers *.Cu F.Paste F.SilkS F.Mask) |
542 |
(net 1 /GND) |
|
543 |
) |
|
544 |
) |
|
545 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
546 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534C7F7E) (tstamp 534C7FE8) |
547 |
(at 68.58 68.58 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
548 |
(descr "Double rangee de contacts 2 x 5 pins") |
549 |
(tags CONN) |
|
550 |
(path /53497310) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
551 |
(fp_text reference P2 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
552 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
553 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
554 |
(fp_text value HC-SR04_PROXSENS (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
555 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
556 |
) |
|
557 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
558 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
559 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
560 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
561 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 1.524 2.286) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
562 |
(layers *.Cu *.Mask F.SilkS) |
563 |
(net 2 /VCC) |
|
564 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
565 |
(pad 2 thru_hole oval (at -1.27 0 270) (size 1.524 2.286) (drill 1.143) |
566 |
(layers *.Cu *.Mask F.SilkS) |
|
567 |
(net 18 N-0000048) |
|
568 |
) |
|
569 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
570 |
(layers *.Cu *.Mask F.SilkS) |
|
571 |
(net 21 N-0000052) |
|
572 |
) |
|
573 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
574 |
(layers *.Cu *.Mask F.SilkS) |
575 |
(net 1 /GND) |
|
576 |
) |
|
577 |
(model pin_array\pins_array_4x1.wrl |
|
578 |
(at (xyz 0 0 0)) |
|
579 |
(scale (xyz 1 1 1)) |
|
580 |
(rotate (xyz 0 0 0)) |
|
581 |
) |
|
582 |
) |
|
583 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
584 |
(module IMU_Mount (layer F.Cu) (tedit 534F2E1F) (tstamp 534F1CEE) |
585 |
(at 55.88 114.3) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
586 |
(path /532A16AB) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
587 |
(fp_text reference U1 (at 0 -2.54) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
588 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
589 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
590 |
(fp_text value IMU_MOUNT (at 0 0) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
591 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
592 |
) |
|
593 |
(fp_line (start -12.7 8.89) (end 12.7 8.89) (layer F.SilkS) (width 0.15)) |
|
594 |
(fp_line (start -12.7 8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
595 |
(fp_line (start 12.7 8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
596 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
597 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
598 |
(fp_line (start 12.7 -8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
599 |
(pad 1 thru_hole circle (at 11.43 2.54) (size 2.032 2.032) (drill 1.143) |
600 |
(layers *.Cu *.Mask F.SilkS) |
|
601 |
(net 22 N-0000054) |
|
602 |
) |
|
603 |
(pad 2 thru_hole oval (at 11.43 0) (size 2.032 1.524) (drill 1.143) |
|
604 |
(layers *.Cu *.Mask F.SilkS) |
|
605 |
(net 20 N-0000050) |
|
606 |
) |
|
607 |
(pad 3 thru_hole oval (at 11.43 -2.54) (size 2.032 1.524) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
608 |
(layers *.Cu *.Mask F.SilkS) |
609 |
(net 2 /VCC) |
|
610 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
611 |
(pad 4 thru_hole circle (at 11.43 -5.08) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
612 |
(layers *.Cu *.Mask F.SilkS) |
613 |
(net 1 /GND) |
|
614 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
615 |
(pad 5 thru_hole circle (at -11.43 7.62) (size 2.032 2.032) (drill 1.143) |
616 |
(layers *.Cu *.Mask F.SilkS) |
|
617 |
) |
|
618 |
(pad 6 thru_hole circle (at -11.43 5.08) (size 2.032 2.032) (drill 1.143) |
|
619 |
(layers *.Cu *.Mask F.SilkS) |
|
620 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
621 |
(pad 7 thru_hole oval (at -11.43 2.54) (size 2.032 1.524) (drill 1.143) |
622 |
(layers *.Cu *.Mask F.SilkS) |
|
623 |
) |
|
624 |
(pad 8 thru_hole oval (at -11.43 0) (size 2.032 1.524) (drill 1.143) |
|
625 |
(layers *.Cu *.Mask F.SilkS) |
|
626 |
) |
|
627 |
(pad 9 thru_hole oval (at -11.43 -2.54) (size 2.032 1.524) (drill 1.143) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
628 |
(layers *.Cu *.Mask F.SilkS) |
629 |
) |
|
630 |
(pad 10 thru_hole circle (at -11.43 -5.08) (size 2.032 2.032) (drill 1.143) |
|
631 |
(layers *.Cu *.Mask F.SilkS) |
|
632 |
) |
|
633 |
(pad 11 thru_hole circle (at -11.43 -7.62) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
634 |
(layers *.Cu *.Mask F.SilkS) |
635 |
) |
|
636 |
) |
|
637 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
638 |
(module Arduino_Mega_Shield_Partial (layer F.Cu) (tedit 534F2CAF) (tstamp 534F2CD5) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
639 |
(at 49.53 77.47) |
640 |
(path /532A24F4) |
|
641 |
(fp_text reference U3 (at 0 -2.54) (layer F.SilkS) |
|
642 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
643 |
) |
|
644 |
(fp_text value ARDUINO_MEGA_SHIELD (at 0 0) (layer F.SilkS) |
|
645 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
646 |
) |
|
647 |
(fp_line (start 26.67 -31.75) (end 26.67 48.26) (layer F.SilkS) (width 0.15)) |
|
648 |
(fp_line (start -24.13 48.26) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
649 |
(fp_line (start 26.67 48.26) (end -24.13 48.26) (layer F.SilkS) (width 0.15)) |
|
650 |
(fp_line (start 26.67 -31.75) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
651 |
(pad 1 thru_hole circle (at -22.86 -11.43) (size 2.032 2.032) (drill 1.143) |
652 |
(layers *.Cu *.Mask F.SilkS) |
|
653 |
) |
|
654 |
(pad 2 thru_hole circle (at -22.86 -8.89) (size 2.032 2.032) (drill 1.143) |
|
655 |
(layers *.Cu *.Mask F.SilkS) |
|
656 |
) |
|
657 |
(pad 3 thru_hole oval (at -22.86 -6.35) (size 2.032 1.524) (drill 1.143) |
|
658 |
(layers *.Cu *.Mask F.SilkS) |
|
659 |
(net 25 N-0000080) |
|
660 |
) |
|
661 |
(pad 4 thru_hole oval (at -22.86 -3.81) (size 2.032 1.524) (drill 1.143) |
|
662 |
(layers *.Cu *.Mask F.SilkS) |
|
663 |
(net 1 /GND) |
|
664 |
) |
|
665 |
(pad 5 thru_hole circle (at -22.86 -1.27) (size 2.032 2.032) (drill 1.143) |
|
666 |
(layers *.Cu *.Mask F.SilkS) |
|
667 |
(net 1 /GND) |
|
668 |
) |
|
669 |
(pad 6 thru_hole circle (at -22.86 1.27) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
670 |
(layers *.Cu *.Mask F.SilkS) |
671 |
(net 2 /VCC) |
|
672 |
) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
673 |
(pad 7 thru_hole oval (at -22.86 6.35) (size 2.032 1.524) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
674 |
(layers *.Cu *.Mask F.SilkS) |
675 |
(net 24 N-0000079) |
|
676 |
) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
677 |
(pad 8 thru_hole oval (at -22.86 8.89) (size 2.032 1.524) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
678 |
(layers *.Cu *.Mask F.SilkS) |
679 |
) |
|
680 |
(pad 9 thru_hole circle (at -22.86 11.43) (size 2.032 2.032) (drill 1.143) |
|
681 |
(layers *.Cu *.Mask F.SilkS) |
|
682 |
) |
|
683 |
(pad 10 thru_hole circle (at -22.86 13.97) (size 2.032 2.032) (drill 1.143) |
|
684 |
(layers *.Cu *.Mask F.SilkS) |
|
685 |
) |
|
686 |
(pad 11 thru_hole circle (at -22.86 16.51) (size 2.032 2.032) (drill 1.143) |
|
687 |
(layers *.Cu *.Mask F.SilkS) |
|
688 |
) |
|
689 |
(pad 12 thru_hole circle (at -22.86 19.05) (size 2.032 2.032) (drill 1.143) |
|
690 |
(layers *.Cu *.Mask F.SilkS) |
|
691 |
) |
|
692 |
(pad 13 thru_hole circle (at -22.86 21.59) (size 2.032 2.032) (drill 1.143) |
|
693 |
(layers *.Cu *.Mask F.SilkS) |
|
694 |
) |
|
695 |
(pad 14 thru_hole circle (at -22.86 24.13) (size 2.032 2.032) (drill 1.143) |
|
696 |
(layers *.Cu *.Mask F.SilkS) |
|
697 |
) |
|
698 |
(pad 15 thru_hole circle (at -22.86 29.21) (size 2.032 2.032) (drill 1.143) |
|
699 |
(layers *.Cu *.Mask F.SilkS) |
|
700 |
) |
|
701 |
(pad 16 thru_hole circle (at -22.86 31.75) (size 2.032 2.032) (drill 1.143) |
|
702 |
(layers *.Cu *.Mask F.SilkS) |
|
703 |
) |
|
704 |
(pad 17 thru_hole circle (at -22.86 34.29) (size 2.032 2.032) (drill 1.143) |
|
705 |
(layers *.Cu *.Mask F.SilkS) |
|
706 |
) |
|
707 |
(pad 18 thru_hole circle (at -22.86 36.83) (size 2.032 2.032) (drill 1.143) |
|
708 |
(layers *.Cu *.Mask F.SilkS) |
|
709 |
) |
|
710 |
(pad 19 thru_hole circle (at -22.86 39.37) (size 2.032 2.032) (drill 1.143) |
|
711 |
(layers *.Cu *.Mask F.SilkS) |
|
712 |
) |
|
713 |
(pad 20 thru_hole circle (at -22.86 41.91) (size 2.032 2.032) (drill 1.143) |
|
714 |
(layers *.Cu *.Mask F.SilkS) |
|
715 |
) |
|
716 |
(pad 21 thru_hole circle (at -22.86 44.45) (size 2.032 2.032) (drill 1.143) |
|
717 |
(layers *.Cu *.Mask F.SilkS) |
|
718 |
) |
|
719 |
(pad 23 thru_hole circle (at 25.4 41.91) (size 2.032 2.032) (drill 1.143) |
|
720 |
(layers *.Cu *.Mask F.SilkS) |
|
721 |
(net 22 N-0000054) |
|
722 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
723 |
(pad 24 thru_hole oval (at 25.4 39.37) (size 2.032 1.524) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
724 |
(layers *.Cu *.Mask F.SilkS) |
725 |
(net 20 N-0000050) |
|
726 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
727 |
(pad 25 thru_hole oval (at 25.4 36.83) (size 2.032 1.524) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
728 |
(layers *.Cu *.Mask F.SilkS) |
729 |
(net 16 N-0000034) |
|
730 |
) |
|
731 |
(pad 26 thru_hole circle (at 25.4 34.29) (size 2.032 2.032) (drill 1.143) |
|
732 |
(layers *.Cu *.Mask F.SilkS) |
|
733 |
(net 19 N-000005) |
|
734 |
) |
|
735 |
(pad 27 thru_hole circle (at 25.4 31.75) (size 2.032 2.032) (drill 1.143) |
|
736 |
(layers *.Cu *.Mask F.SilkS) |
|
737 |
) |
|
738 |
(pad 28 thru_hole circle (at 25.4 29.21) (size 2.032 2.032) (drill 1.143) |
|
739 |
(layers *.Cu *.Mask F.SilkS) |
|
740 |
) |
|
741 |
(pad 29 thru_hole circle (at 25.4 26.67) (size 2.032 2.032) (drill 1.143) |
|
742 |
(layers *.Cu *.Mask F.SilkS) |
|
743 |
) |
|
744 |
(pad 30 thru_hole circle (at 25.4 24.13) (size 2.032 2.032) (drill 1.143) |
|
745 |
(layers *.Cu *.Mask F.SilkS) |
|
746 |
) |
|
747 |
(pad 31 thru_hole circle (at 25.4 19.05) (size 2.032 2.032) (drill 1.143) |
|
748 |
(layers *.Cu *.Mask F.SilkS) |
|
749 |
) |
|
750 |
(pad 32 thru_hole circle (at 25.4 16.51) (size 2.032 2.032) (drill 1.143) |
|
751 |
(layers *.Cu *.Mask F.SilkS) |
|
752 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
753 |
(pad 33 thru_hole oval (at 25.4 13.97) (size 1.524 2.032) (drill 1.143) |
754 |
(layers *.Cu *.Mask F.SilkS) |
|
755 |
) |
|
756 |
(pad 34 thru_hole oval (at 25.4 11.43) (size 1.524 2.032) (drill 1.143) |
|
757 |
(layers *.Cu *.Mask F.SilkS) |
|
758 |
) |
|
759 |
(pad 35 thru_hole oval (at 25.4 8.89) (size 1.524 2.032) (drill 1.143) |
|
760 |
(layers *.Cu *.Mask F.SilkS) |
|
761 |
) |
|
762 |
(pad 36 thru_hole oval (at 25.4 6.35) (size 1.524 2.032) (drill 1.143) |
|
763 |
(layers *.Cu *.Mask F.SilkS) |
|
764 |
) |
|
765 |
(pad 37 thru_hole oval (at 25.4 3.81) (size 1.524 2.032) (drill 1.143) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
766 |
(layers *.Cu *.Mask F.SilkS) |
767 |
) |
|
768 |
(pad 38 thru_hole circle (at 25.4 1.27) (size 2.032 2.032) (drill 1.143) |
|
769 |
(layers *.Cu *.Mask F.SilkS) |
|
770 |
) |
|
771 |
(pad 39 thru_hole circle (at 25.4 -2.54) (size 2.032 2.032) (drill 1.143) |
|
772 |
(layers *.Cu *.Mask F.SilkS) |
|
773 |
) |
|
774 |
(pad 40 thru_hole circle (at 25.4 -5.08) (size 2.032 2.032) (drill 1.143) |
|
775 |
(layers *.Cu *.Mask F.SilkS) |
|
776 |
) |
|
777 |
(pad 41 thru_hole circle (at 25.4 -7.62) (size 2.032 2.032) (drill 1.143) |
|
778 |
(layers *.Cu *.Mask F.SilkS) |
|
779 |
) |
|
780 |
(pad 42 thru_hole circle (at 25.4 -10.16) (size 2.032 2.032) (drill 1.143) |
|
781 |
(layers *.Cu *.Mask F.SilkS) |
|
782 |
) |
|
783 |
(pad 43 thru_hole circle (at 25.4 -12.7) (size 2.032 2.032) (drill 1.143) |
|
784 |
(layers *.Cu *.Mask F.SilkS) |
|
785 |
(net 21 N-0000052) |
|
786 |
) |
|
787 |
(pad 44 thru_hole circle (at 25.4 -15.24) (size 2.032 2.032) (drill 1.143) |
|
788 |
(layers *.Cu *.Mask F.SilkS) |
|
789 |
(net 18 N-0000048) |
|
790 |
) |
|
791 |
(pad 45 thru_hole circle (at 25.4 -17.78) (size 2.032 2.032) (drill 1.143) |
|
792 |
(layers *.Cu *.Mask F.SilkS) |
|
793 |
(net 1 /GND) |
|
794 |
) |
|
795 |
(pad 46 thru_hole circle (at 25.4 -20.32) (size 2.032 2.032) (drill 1.143) |
|
796 |
(layers *.Cu *.Mask F.SilkS) |
|
797 |
(net 25 N-0000080) |
|
798 |
) |
|
799 |
(pad 22 thru_hole circle (at -22.86 46.99) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
800 |
(layers *.Cu *.Mask F.SilkS) |
801 |
) |
|
802 |
) |
|
803 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
804 |
(module R3 (layer F.Cu) (tedit 534F3037) (tstamp 534C80B7) |
805 |
(at 48.26 73.66 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
806 |
(descr "Resitance 3 pas") |
807 |
(tags R) |
|
808 |
(path /53496D70) |
|
809 |
(autoplace_cost180 10) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
810 |
(fp_text reference R3 (at 0 0.127 270) (layer F.SilkS) hide |
811 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
|
812 |
) |
|
813 |
(fp_text value 10k (at 0 0.127 270) (layer F.SilkS) |
|
814 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
|
815 |
) |
|
816 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
817 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
818 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
819 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
820 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
821 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
822 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
823 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
824 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 1.524 2.032) (drill 1.143) |
|
825 |
(layers *.Cu *.Mask F.SilkS) |
|
826 |
(net 1 /GND) |
|
827 |
) |
|
828 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
829 |
(layers *.Cu *.Mask F.SilkS) |
|
830 |
(net 4 N-0000017) |
|
831 |
) |
|
832 |
(model discret/resistor.wrl |
|
833 |
(at (xyz 0 0 0)) |
|
834 |
(scale (xyz 0.3 0.3 0.3)) |
|
835 |
(rotate (xyz 0 0 0)) |
|
836 |
) |
|
837 |
) |
|
838 |
||
839 |
(module R3 (layer F.Cu) (tedit 534F3031) (tstamp 534F21B5) |
|
840 |
(at 45.72 73.66 90) |
|
841 |
(descr "Resitance 3 pas") |
|
842 |
(tags R) |
|
843 |
(path /53496D82) |
|
844 |
(autoplace_cost180 10) |
|
845 |
(fp_text reference R4 (at 0 0.127 90) (layer F.SilkS) hide |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
846 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
847 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
848 |
(fp_text value 10k (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
849 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
850 |
) |
|
851 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
852 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
853 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
854 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
855 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
856 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
857 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
858 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
859 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
860 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
861 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
862 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
863 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
864 |
(layers *.Cu *.Mask F.SilkS) |
865 |
(net 1 /GND) |
|
866 |
) |
|
867 |
(model discret/resistor.wrl |
|
868 |
(at (xyz 0 0 0)) |
|
869 |
(scale (xyz 0.3 0.3 0.3)) |
|
870 |
(rotate (xyz 0 0 0)) |
|
871 |
) |
|
872 |
) |
|
873 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
874 |
(module pin_array_4x2 (layer F.Cu) (tedit 534F3091) (tstamp 534C8C00) |
875 |
(at 62.23 92.71 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
876 |
(descr "Double rangee de contacts 2 x 4 pins") |
877 |
(tags CONN) |
|
878 |
(path /53496DB9) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
879 |
(fp_text reference P18 (at 0 -3.81 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
880 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
881 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
882 |
(fp_text value "ESC P & G" (at 0 3.81 90) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
883 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
884 |
) |
|
885 |
(fp_line (start -5.08 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
886 |
(fp_line (start 5.08 -2.54) (end 5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
887 |
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
888 |
(fp_line (start -5.08 2.54) (end -5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
889 |
(pad 1 thru_hole circle (at -3.81 1.27 90) (size 2.032 2.032) (drill 1.143) |
890 |
(layers *.Cu *.Mask F.SilkS) |
|
891 |
(net 2 /VCC) |
|
892 |
) |
|
893 |
(pad 2 thru_hole circle (at -3.81 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
894 |
(layers *.Cu *.Mask F.SilkS) |
|
895 |
(net 1 /GND) |
|
896 |
) |
|
897 |
(pad 3 thru_hole circle (at -1.27 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
898 |
(layers *.Cu *.Mask F.SilkS) |
|
899 |
(net 2 /VCC) |
|
900 |
) |
|
901 |
(pad 4 thru_hole circle (at -1.27 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
902 |
(layers *.Cu *.Mask F.SilkS) |
|
903 |
(net 1 /GND) |
|
904 |
) |
|
905 |
(pad 5 thru_hole circle (at 1.27 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
906 |
(layers *.Cu *.Mask F.SilkS) |
|
907 |
(net 2 /VCC) |
|
908 |
) |
|
909 |
(pad 6 thru_hole circle (at 1.27 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
910 |
(layers *.Cu *.Mask F.SilkS) |
|
911 |
(net 1 /GND) |
|
912 |
) |
|
913 |
(pad 7 thru_hole circle (at 3.81 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
914 |
(layers *.Cu *.Mask F.SilkS) |
|
915 |
(net 2 /VCC) |
|
916 |
) |
|
917 |
(pad 8 thru_hole circle (at 3.81 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
918 |
(layers *.Cu *.Mask F.SilkS) |
919 |
(net 1 /GND) |
|
920 |
) |
|
921 |
(model pin_array/pins_array_4x2.wrl |
|
922 |
(at (xyz 0 0 0)) |
|
923 |
(scale (xyz 1 1 1)) |
|
924 |
(rotate (xyz 0 0 0)) |
|
925 |
) |
|
926 |
) |
|
927 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
928 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534F3167) (tstamp 5349B010) |
929 |
(at 66.04 92.71 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
930 |
(descr "Double rangee de contacts 2 x 5 pins") |
931 |
(tags CONN) |
|
932 |
(path /53496DBF) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
933 |
(fp_text reference P17 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
934 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
935 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
936 |
(fp_text value "ESC Sig" (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
937 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
938 |
) |
|
939 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
940 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
941 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
942 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
943 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 2.032 1.524) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
944 |
(layers *.Cu *.Mask F.SilkS) |
945 |
(net 17 N-000004) |
|
946 |
) |
|
947 |
(pad 2 thru_hole circle (at -1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
948 |
(layers *.Cu *.Mask F.SilkS) |
|
949 |
(net 15 N-000003) |
|
950 |
) |
|
951 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) |
|
952 |
(layers *.Cu *.Mask F.SilkS) |
|
953 |
(net 7 N-000002) |
|
954 |
) |
|
955 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
956 |
(layers *.Cu *.Mask F.SilkS) |
957 |
(net 3 N-000001) |
|
958 |
) |
|
959 |
(model pin_array\pins_array_4x1.wrl |
|
960 |
(at (xyz 0 0 0)) |
|
961 |
(scale (xyz 1 1 1)) |
|
962 |
(rotate (xyz 0 0 0)) |
|
963 |
) |
|
964 |
) |
|
965 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
966 |
(module D3 (layer F.Cu) (tedit 534F3058) (tstamp 534EE282) |
967 |
(at 34.29 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
968 |
(descr "Diode 3 pas") |
969 |
(tags "DIODE DEV") |
|
970 |
(path /53496D88) |
|
971 |
(fp_text reference D1 (at 0 0 90) (layer F.SilkS) |
|
972 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
973 |
) |
|
974 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
975 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
976 |
) |
|
977 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
978 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
979 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
980 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
981 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
982 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
983 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
984 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
985 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
986 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
987 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
988 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
989 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
990 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
991 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
992 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
993 |
(net 14 N-0000026) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
994 |
) |
995 |
(model discret/diode.wrl |
|
996 |
(at (xyz 0 0 0)) |
|
997 |
(scale (xyz 0.3 0.3 0.3)) |
|
998 |
(rotate (xyz 0 0 0)) |
|
999 |
) |
|
1000 |
) |
|
1001 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1002 |
(module D3 (layer F.Cu) (tedit 534F3068) (tstamp 5349B03C) |
1003 |
(at 41.91 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1004 |
(descr "Diode 3 pas") |
1005 |
(tags "DIODE DEV") |
|
1006 |
(path /53496D8E) |
|
1007 |
(fp_text reference D4 (at 0 0 90) (layer F.SilkS) |
|
1008 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1009 |
) |
|
1010 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1011 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1012 |
) |
|
1013 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1014 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1015 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1016 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1017 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1018 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1019 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1020 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1021 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1022 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1023 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1024 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1025 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1026 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1027 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1028 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1029 |
(net 13 N-0000025) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1030 |
) |
1031 |
(model discret/diode.wrl |
|
1032 |
(at (xyz 0 0 0)) |
|
1033 |
(scale (xyz 0.3 0.3 0.3)) |
|
1034 |
(rotate (xyz 0 0 0)) |
|
1035 |
) |
|
1036 |
) |
|
1037 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1038 |
(module D3 (layer F.Cu) (tedit 534F305E) (tstamp 5349B04C) |
1039 |
(at 36.83 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1040 |
(descr "Diode 3 pas") |
1041 |
(tags "DIODE DEV") |
|
1042 |
(path /53496D94) |
|
1043 |
(fp_text reference D2 (at 0 0 90) (layer F.SilkS) |
|
1044 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1045 |
) |
|
1046 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1047 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1048 |
) |
|
1049 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1050 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1051 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1052 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1053 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1054 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1055 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1056 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1057 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1058 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1059 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1060 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1061 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1062 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
1063 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1064 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1065 |
(net 11 N-0000023) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1066 |
) |
1067 |
(model discret/diode.wrl |
|
1068 |
(at (xyz 0 0 0)) |
|
1069 |
(scale (xyz 0.3 0.3 0.3)) |
|
1070 |
(rotate (xyz 0 0 0)) |
|
1071 |
) |
|
1072 |
) |
|
1073 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1074 |
(module D3 (layer F.Cu) (tedit 534F3063) (tstamp 5349B05C) |
1075 |
(at 39.37 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1076 |
(descr "Diode 3 pas") |
1077 |
(tags "DIODE DEV") |
|
1078 |
(path /53496D9A) |
|
1079 |
(fp_text reference D3 (at 0 0 90) (layer F.SilkS) |
|
1080 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1081 |
) |
|
1082 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1083 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1084 |
) |
|
1085 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1086 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1087 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1088 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1089 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1090 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1091 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1092 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1093 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1094 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1095 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1096 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1097 |
(net 12 N-0000024) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1098 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
1099 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1100 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1101 |
(net 10 N-0000022) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1102 |
) |
1103 |
(model discret/diode.wrl |
|
1104 |
(at (xyz 0 0 0)) |
|
1105 |
(scale (xyz 0.3 0.3 0.3)) |
|
1106 |
(rotate (xyz 0 0 0)) |
|
1107 |
) |
|
1108 |
) |
|
1109 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1110 |
(module D3 (layer F.Cu) (tedit 534F306C) (tstamp 5349B06C) |
1111 |
(at 44.45 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1112 |
(descr "Diode 3 pas") |
1113 |
(tags "DIODE DEV") |
|
1114 |
(path /53496DA0) |
|
1115 |
(fp_text reference D5 (at 0 0 90) (layer F.SilkS) |
|
1116 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1117 |
) |
|
1118 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1119 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1120 |
) |
|
1121 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1122 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1123 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1124 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1125 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1126 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1127 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1128 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1129 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1130 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1131 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1132 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1133 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1134 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
1135 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1136 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1137 |
(net 9 N-0000021) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1138 |
) |
1139 |
(model discret/diode.wrl |
|
1140 |
(at (xyz 0 0 0)) |
|
1141 |
(scale (xyz 0.3 0.3 0.3)) |
|
1142 |
(rotate (xyz 0 0 0)) |
|
1143 |
) |
|
1144 |
) |
|
1145 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1146 |
(module D3 (layer F.Cu) (tedit 534C9281) (tstamp 5349B07C) |
|
50
by dan
finnished connecting all of the components together #=O) |
1147 |
(at 46.99 87.63 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1148 |
(descr "Diode 3 pas") |
1149 |
(tags "DIODE DEV") |
|
1150 |
(path /53496DA6) |
|
1151 |
(fp_text reference D6 (at 0 0 90) (layer F.SilkS) |
|
1152 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1153 |
) |
|
1154 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1155 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1156 |
) |
|
1157 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1158 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1159 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1160 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1161 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1162 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1163 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1164 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1165 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1166 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1167 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1168 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1169 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1170 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1171 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1172 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1173 |
(net 8 N-0000020) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1174 |
) |
1175 |
(model discret/diode.wrl |
|
1176 |
(at (xyz 0 0 0)) |
|
1177 |
(scale (xyz 0.3 0.3 0.3)) |
|
1178 |
(rotate (xyz 0 0 0)) |
|
1179 |
) |
|
1180 |
) |
|
1181 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1182 |
(module D3 (layer F.Cu) (tedit 534F3072) (tstamp 5349B08C) |
1183 |
(at 49.53 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1184 |
(descr "Diode 3 pas") |
1185 |
(tags "DIODE DEV") |
|
1186 |
(path /53496DAC) |
|
1187 |
(fp_text reference D7 (at 0 0 90) (layer F.SilkS) |
|
1188 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1189 |
) |
|
1190 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1191 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1192 |
) |
|
1193 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1194 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1195 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1196 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1197 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1198 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1199 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1200 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1201 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1202 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1203 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1204 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1205 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1206 |
) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1207 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1208 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1209 |
(net 6 N-0000019) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1210 |
) |
1211 |
(model discret/diode.wrl |
|
1212 |
(at (xyz 0 0 0)) |
|
1213 |
(scale (xyz 0.3 0.3 0.3)) |
|
1214 |
(rotate (xyz 0 0 0)) |
|
1215 |
) |
|
1216 |
) |
|
1217 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1218 |
(module D3 (layer F.Cu) (tedit 534F3077) (tstamp 5349B09C) |
1219 |
(at 52.07 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1220 |
(descr "Diode 3 pas") |
1221 |
(tags "DIODE DEV") |
|
1222 |
(path /53496DB2) |
|
1223 |
(fp_text reference D8 (at 0 0 90) (layer F.SilkS) |
|
1224 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1225 |
) |
|
1226 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
1227 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
1228 |
) |
|
1229 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1230 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1231 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
1232 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1233 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
1234 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1235 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
1236 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
1237 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
1238 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1239 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1240 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1241 |
(net 4 N-0000017) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1242 |
) |
|
50
by dan
finnished connecting all of the components together #=O) |
1243 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1244 |
(layers *.Cu *.Mask F.SilkS) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1245 |
(net 5 N-0000018) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1246 |
) |
1247 |
(model discret/diode.wrl |
|
1248 |
(at (xyz 0 0 0)) |
|
1249 |
(scale (xyz 0.3 0.3 0.3)) |
|
1250 |
(rotate (xyz 0 0 0)) |
|
1251 |
) |
|
1252 |
) |
|
1253 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1254 |
(module Arduino_Mini_Pro_Mount (layer F.Cu) (tedit 534F322E) (tstamp 534F32C6) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1255 |
(at 49.53 71.12 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1256 |
(path /53497285) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1257 |
(fp_text reference U4 (at -1.27 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1258 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1259 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1260 |
(fp_text value ARDUINO_MINI_PRO_MOUNT (at 1.27 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1261 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1262 |
) |
|
1263 |
(fp_line (start -10.16 15.24) (end 7.62 15.24) (layer F.SilkS) (width 0.15)) |
|
1264 |
(fp_line (start 7.62 15.24) (end 7.62 -17.78) (layer F.SilkS) (width 0.15)) |
|
1265 |
(fp_line (start 7.62 -17.78) (end -10.16 -17.78) (layer F.SilkS) (width 0.15)) |
|
1266 |
(fp_line (start -10.16 -17.78) (end -10.16 15.24) (layer F.SilkS) (width 0.15)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1267 |
(pad 1 thru_hole circle (at -8.89 -13.97 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1268 |
(layers *.Cu *.Mask F.SilkS) |
1269 |
(net 16 N-0000034) |
|
1270 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1271 |
(pad 2 thru_hole circle (at -8.89 -11.43 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1272 |
(layers *.Cu *.Mask F.SilkS) |
1273 |
(net 19 N-000005) |
|
1274 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1275 |
(pad 3 thru_hole circle (at -8.89 -8.89 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1276 |
(layers *.Cu *.Mask F.SilkS) |
1277 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1278 |
(pad 4 thru_hole circle (at -8.89 -6.35 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1279 |
(layers *.Cu *.Mask F.SilkS) |
1280 |
(net 1 /GND) |
|
1281 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1282 |
(pad 5 thru_hole circle (at -8.89 -3.81 90) (size 2.032 2.032) (drill 1.143) |
1283 |
(layers *.Cu *.Mask F.SilkS) |
|
1284 |
(net 12 N-0000024) |
|
1285 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1286 |
(pad 6 thru_hole circle (at -8.89 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1287 |
(layers *.Cu *.Mask F.SilkS) |
1288 |
(net 4 N-0000017) |
|
1289 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1290 |
(pad 7 thru_hole circle (at -8.89 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1291 |
(layers *.Cu *.Mask F.SilkS) |
1292 |
(net 3 N-000001) |
|
1293 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1294 |
(pad 8 thru_hole circle (at -8.89 3.81 90) (size 2.032 2.032) (drill 1.143) |
1295 |
(layers *.Cu *.Mask F.SilkS) |
|
1296 |
(net 7 N-000002) |
|
1297 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1298 |
(pad 9 thru_hole circle (at -8.89 6.35 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1299 |
(layers *.Cu *.Mask F.SilkS) |
1300 |
(net 15 N-000003) |
|
1301 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1302 |
(pad 10 thru_hole circle (at -8.89 8.89 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1303 |
(layers *.Cu *.Mask F.SilkS) |
1304 |
(net 17 N-000004) |
|
1305 |
) |
|
1306 |
(pad 11 thru_hole oval (at -8.89 11.43 90) (size 1.524 2.032) (drill 1.143) |
|
1307 |
(layers *.Cu *.Mask F.SilkS) |
|
1308 |
) |
|
1309 |
(pad 12 thru_hole oval (at -8.89 13.97 90) (size 1.524 2.032) (drill 1.143) |
|
1310 |
(layers *.Cu *.Mask F.SilkS) |
|
1311 |
) |
|
1312 |
(pad 13 thru_hole circle (at 6.35 13.97 90) (size 2.032 2.032) (drill 1.143) |
|
1313 |
(layers *.Cu *.Mask F.SilkS) |
|
1314 |
) |
|
1315 |
(pad 14 thru_hole circle (at 6.35 11.43 90) (size 2.032 2.032) (drill 1.143) |
|
1316 |
(layers *.Cu *.Mask F.SilkS) |
|
1317 |
) |
|
1318 |
(pad 15 thru_hole circle (at 6.35 8.89 90) (size 2.032 2.032) (drill 1.143) |
|
1319 |
(layers *.Cu *.Mask F.SilkS) |
|
1320 |
) |
|
1321 |
(pad 16 thru_hole circle (at 6.35 6.35 90) (size 2.032 2.032) (drill 1.143) |
|
1322 |
(layers *.Cu *.Mask F.SilkS) |
|
1323 |
) |
|
1324 |
(pad 17 thru_hole circle (at 6.35 3.81 90) (size 2.032 2.032) (drill 1.143) |
|
1325 |
(layers *.Cu *.Mask F.SilkS) |
|
1326 |
) |
|
1327 |
(pad 18 thru_hole circle (at 6.35 1.27 90) (size 2.032 2.032) (drill 1.143) |
|
1328 |
(layers *.Cu *.Mask F.SilkS) |
|
1329 |
) |
|
1330 |
(pad 19 thru_hole circle (at 6.35 -1.27 90) (size 2.032 2.032) (drill 1.143) |
|
1331 |
(layers *.Cu *.Mask F.SilkS) |
|
1332 |
) |
|
1333 |
(pad 20 thru_hole circle (at 6.35 -3.81 90) (size 2.032 2.032) (drill 1.143) |
|
1334 |
(layers *.Cu *.Mask F.SilkS) |
|
1335 |
) |
|
1336 |
(pad 21 thru_hole circle (at 6.35 -6.35 90) (size 2.032 2.032) (drill 1.143) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1337 |
(layers *.Cu *.Mask F.SilkS) |
1338 |
(net 2 /VCC) |
|
1339 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1340 |
(pad 22 thru_hole circle (at 6.35 -8.89 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1341 |
(layers *.Cu *.Mask F.SilkS) |
1342 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1343 |
(pad 23 thru_hole circle (at 6.35 -11.43 90) (size 2.032 2.032) (drill 1.143) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1344 |
(layers *.Cu *.Mask F.SilkS) |
1345 |
(net 1 /GND) |
|
1346 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1347 |
(pad 24 thru_hole circle (at 6.35 -13.97 90) (size 2.032 2.032) (drill 1.143) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1348 |
(layers *.Cu *.Mask F.SilkS) |
1349 |
) |
|
1350 |
) |
|
1351 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1352 |
(module 9x3_Conn_Block (layer F.Cu) (tedit 534C7723) (tstamp 534C9726) |
|
50
by dan
finnished connecting all of the components together #=O) |
1353 |
(at 44.45 96.52 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1354 |
(path /53497B7A) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1355 |
(fp_text reference U5 (at -5.08 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1356 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1357 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1358 |
(fp_text value 9X3_CONN_BLOCK (at 5.08 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1359 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1360 |
) |
|
1361 |
(fp_line (start -3.81 -11.43) (end 3.81 -11.43) (layer F.SilkS) (width 0.15)) |
|
1362 |
(fp_line (start 3.81 -11.43) (end 3.81 11.43) (layer F.SilkS) (width 0.15)) |
|
1363 |
(fp_line (start 3.81 11.43) (end -3.81 11.43) (layer F.SilkS) (width 0.15)) |
|
1364 |
(fp_line (start -3.81 11.43) (end -3.81 -11.43) (layer F.SilkS) (width 0.15)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1365 |
(pad 1 thru_hole circle (at -2.54 -10.16 90) (size 2.032 2.032) (drill 1.143) |
1366 |
(layers *.Cu *.Mask F.SilkS) |
|
1367 |
(net 1 /GND) |
|
1368 |
) |
|
1369 |
(pad 2 thru_hole circle (at -2.54 -7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1370 |
(layers *.Cu *.Mask F.SilkS) |
|
1371 |
(net 1 /GND) |
|
1372 |
) |
|
1373 |
(pad 3 thru_hole circle (at -2.54 -5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1374 |
(layers *.Cu *.Mask F.SilkS) |
|
1375 |
(net 1 /GND) |
|
1376 |
) |
|
1377 |
(pad 4 thru_hole circle (at -2.54 -2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1378 |
(layers *.Cu *.Mask F.SilkS) |
|
1379 |
(net 1 /GND) |
|
1380 |
) |
|
1381 |
(pad 5 thru_hole circle (at -2.54 0 90) (size 2.032 2.032) (drill 1.143) |
|
1382 |
(layers *.Cu *.Mask F.SilkS) |
|
1383 |
(net 1 /GND) |
|
1384 |
) |
|
1385 |
(pad 6 thru_hole circle (at -2.54 2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1386 |
(layers *.Cu *.Mask F.SilkS) |
|
1387 |
(net 1 /GND) |
|
1388 |
) |
|
1389 |
(pad 7 thru_hole circle (at -2.54 5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1390 |
(layers *.Cu *.Mask F.SilkS) |
|
1391 |
(net 1 /GND) |
|
1392 |
) |
|
1393 |
(pad 8 thru_hole circle (at -2.54 7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1394 |
(layers *.Cu *.Mask F.SilkS) |
|
1395 |
(net 1 /GND) |
|
1396 |
) |
|
1397 |
(pad 9 thru_hole circle (at -2.54 10.16 90) (size 2.032 2.032) (drill 1.143) |
|
1398 |
(layers *.Cu *.Mask F.SilkS) |
|
1399 |
(net 1 /GND) |
|
1400 |
) |
|
1401 |
(pad 10 thru_hole circle (at 0 -10.16 90) (size 2.032 2.032) (drill 1.143) |
|
1402 |
(layers *.Cu *.Mask F.SilkS) |
|
1403 |
(net 2 /VCC) |
|
1404 |
) |
|
1405 |
(pad 11 thru_hole circle (at 0 -7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1406 |
(layers *.Cu *.Mask F.SilkS) |
|
1407 |
(net 2 /VCC) |
|
1408 |
) |
|
1409 |
(pad 12 thru_hole circle (at 0 -5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1410 |
(layers *.Cu *.Mask F.SilkS) |
|
1411 |
(net 2 /VCC) |
|
1412 |
) |
|
1413 |
(pad 13 thru_hole circle (at 0 -2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1414 |
(layers *.Cu *.Mask F.SilkS) |
|
1415 |
(net 2 /VCC) |
|
1416 |
) |
|
1417 |
(pad 14 thru_hole circle (at 0 0 90) (size 2.032 2.032) (drill 1.143) |
|
1418 |
(layers *.Cu *.Mask F.SilkS) |
|
1419 |
(net 2 /VCC) |
|
1420 |
) |
|
1421 |
(pad 15 thru_hole circle (at 0 2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1422 |
(layers *.Cu *.Mask F.SilkS) |
|
1423 |
(net 2 /VCC) |
|
1424 |
) |
|
1425 |
(pad 16 thru_hole circle (at 0 5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1426 |
(layers *.Cu *.Mask F.SilkS) |
|
1427 |
(net 2 /VCC) |
|
1428 |
) |
|
1429 |
(pad 17 thru_hole circle (at 0 7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1430 |
(layers *.Cu *.Mask F.SilkS) |
|
1431 |
(net 2 /VCC) |
|
1432 |
) |
|
1433 |
(pad 18 thru_hole circle (at 0 10.16 90) (size 2.032 2.032) (drill 1.143) |
|
1434 |
(layers *.Cu *.Mask F.SilkS) |
|
1435 |
(net 2 /VCC) |
|
1436 |
) |
|
1437 |
(pad 19 thru_hole circle (at 2.54 -10.16 90) (size 2.032 2.032) (drill 1.143) |
|
1438 |
(layers *.Cu *.Mask F.SilkS) |
|
1439 |
(net 14 N-0000026) |
|
1440 |
) |
|
1441 |
(pad 20 thru_hole circle (at 2.54 -7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1442 |
(layers *.Cu *.Mask F.SilkS) |
|
1443 |
(net 11 N-0000023) |
|
1444 |
) |
|
1445 |
(pad 21 thru_hole circle (at 2.54 -5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1446 |
(layers *.Cu *.Mask F.SilkS) |
|
1447 |
(net 10 N-0000022) |
|
1448 |
) |
|
1449 |
(pad 22 thru_hole circle (at 2.54 -2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1450 |
(layers *.Cu *.Mask F.SilkS) |
|
1451 |
(net 13 N-0000025) |
|
1452 |
) |
|
1453 |
(pad 23 thru_hole circle (at 2.54 0 90) (size 2.032 2.032) (drill 1.143) |
|
1454 |
(layers *.Cu *.Mask F.SilkS) |
|
1455 |
(net 9 N-0000021) |
|
1456 |
) |
|
1457 |
(pad 24 thru_hole circle (at 2.54 2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1458 |
(layers *.Cu *.Mask F.SilkS) |
|
1459 |
(net 8 N-0000020) |
|
1460 |
) |
|
1461 |
(pad 25 thru_hole circle (at 2.54 5.08 90) (size 2.032 2.032) (drill 1.143) |
|
1462 |
(layers *.Cu *.Mask F.SilkS) |
|
1463 |
(net 6 N-0000019) |
|
1464 |
) |
|
1465 |
(pad 26 thru_hole circle (at 2.54 7.62 90) (size 2.032 2.032) (drill 1.143) |
|
1466 |
(layers *.Cu *.Mask F.SilkS) |
|
1467 |
(net 5 N-0000018) |
|
1468 |
) |
|
1469 |
(pad 27 thru_hole circle (at 2.54 10.16 90) (size 2.032 2.032) (drill 1.143) |
|
1470 |
(layers *.Cu *.Mask F.SilkS) |
|
1471 |
) |
|
1472 |
) |
|
1473 |
||
1474 |
(module LM78XXV (layer F.Cu) (tedit 534C7888) (tstamp 5345C7C5) |
|
1475 |
(at 36.83 114.3 90) |
|
1476 |
(descr "Regulateur TO220 serie LM78xx") |
|
1477 |
(tags "TR TO220") |
|
1478 |
(path /5320D1B3) |
|
1479 |
(fp_text reference U2 (at 3.81 0 180) (layer F.SilkS) |
|
1480 |
(effects (font (size 1.524 1.016) (thickness 0.2032))) |
|
1481 |
) |
|
1482 |
(fp_text value 7805 (at -3.175 -0.635 180) (layer F.SilkS) |
|
1483 |
(effects (font (size 1.524 1.016) (thickness 0.2032))) |
|
1484 |
) |
|
1485 |
(fp_line (start 1.905 -4.445) (end 2.54 -4.445) (layer F.SilkS) (width 0.254)) |
|
1486 |
(fp_line (start 2.54 -4.445) (end 2.54 4.445) (layer F.SilkS) (width 0.254)) |
|
1487 |
(fp_line (start 2.54 4.445) (end 1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1488 |
(fp_line (start -1.905 -4.445) (end 1.905 -4.445) (layer F.SilkS) (width 0.254)) |
|
1489 |
(fp_line (start 1.905 -4.445) (end 1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1490 |
(fp_line (start 1.905 4.445) (end -1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1491 |
(fp_line (start -1.905 4.445) (end -1.905 -4.445) (layer F.SilkS) (width 0.254)) |
|
1492 |
(pad VI thru_hole circle (at 0 -2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1493 |
(layers *.Cu *.Mask F.SilkS) |
|
1494 |
(net 23 N-0000060) |
|
1495 |
) |
|
1496 |
(pad GND thru_hole circle (at 0 0 90) (size 2.032 2.032) (drill 1.143) |
|
1497 |
(layers *.Cu *.Mask F.SilkS) |
|
1498 |
(net 1 /GND) |
|
1499 |
) |
|
1500 |
(pad VO thru_hole circle (at 0 2.54 90) (size 2.032 2.032) (drill 1.143) |
|
1501 |
(layers *.Cu *.Mask F.SilkS) |
|
1502 |
(net 2 /VCC) |
|
1503 |
) |
|
1504 |
) |
|
1505 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1506 |
(segment (start 31.75 67.31) (end 31.75 67.31) (width 0.381) (layer B.Cu) (net 0) (tstamp 534F2520)) |
1507 |
(segment (start 48.26 69.85) (end 52.07 73.66) (width 0.381) (layer B.Cu) (net 1)) |
|
1508 |
(segment (start 67.31 104.14) (end 67.31 109.22) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3283)) |
|
1509 |
(segment (start 68.58 102.87) (end 67.31 104.14) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3282)) |
|
1510 |
(segment (start 68.58 95.25) (end 68.58 102.87) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3281)) |
|
1511 |
(segment (start 71.12 92.71) (end 68.58 95.25) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3280)) |
|
1512 |
(segment (start 71.12 80.01) (end 71.12 92.71) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327F)) |
|
1513 |
(segment (start 64.77 73.66) (end 71.12 80.01) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327E)) |
|
1514 |
(segment (start 52.07 73.66) (end 64.77 73.66) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327D)) |
|
1515 |
(segment (start 48.26 115.57) (end 43.18 115.57) (width 0.381) (layer B.Cu) (net 1)) |
|
1516 |
(segment (start 43.18 115.57) (end 39.37 119.38) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2F0F)) |
|
1517 |
(segment (start 39.37 119.38) (end 36.83 119.38) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2F10)) |
|
1518 |
(segment (start 67.31 109.22) (end 68.58 109.22) (width 0.381) (layer B.Cu) (net 1)) |
|
1519 |
(segment (start 62.23 115.57) (end 48.26 115.57) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF6)) |
|
1520 |
(segment (start 64.77 113.03) (end 62.23 115.57) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF4)) |
|
1521 |
(segment (start 68.58 113.03) (end 64.77 113.03) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF3)) |
|
1522 |
(segment (start 69.85 111.76) (end 68.58 113.03) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF2)) |
|
1523 |
(segment (start 69.85 110.49) (end 69.85 111.76) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF1)) |
|
1524 |
(segment (start 68.58 109.22) (end 69.85 110.49) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF0)) |
|
1525 |
(segment (start 36.83 110.49) (end 36.83 109.22) (width 0.381) (layer B.Cu) (net 1)) |
|
1526 |
(segment (start 36.83 109.22) (end 29.21 101.6) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE6)) |
|
1527 |
(segment (start 25.4 76.2) (end 26.67 76.2) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EED)) |
|
1528 |
(segment (start 24.13 77.47) (end 25.4 76.2) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEC)) |
|
1529 |
(segment (start 24.13 83.82) (end 24.13 77.47) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEB)) |
|
1530 |
(segment (start 25.4 85.09) (end 24.13 83.82) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEA)) |
|
1531 |
(segment (start 27.94 85.09) (end 25.4 85.09) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE9)) |
|
1532 |
(segment (start 29.21 86.36) (end 27.94 85.09) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE8)) |
|
1533 |
(segment (start 29.21 101.6) (end 29.21 86.36) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE7)) |
|
1534 |
(segment (start 39.37 106.68) (end 39.37 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2B87)) |
|
1535 |
(segment (start 36.83 109.22) (end 39.37 106.68) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2B83)) |
|
1536 |
(segment (start 60.96 96.52) (end 60.96 93.98) (width 0.381) (layer B.Cu) (net 1)) |
|
1537 |
(segment (start 60.96 93.98) (end 60.96 91.44) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A13)) |
|
1538 |
(segment (start 60.96 91.44) (end 60.96 88.9) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A14)) |
|
1539 |
(segment (start 34.29 99.06) (end 36.83 99.06) (width 0.381) (layer B.Cu) (net 1)) |
|
1540 |
(segment (start 36.83 99.06) (end 39.37 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A06)) |
|
1541 |
(segment (start 39.37 99.06) (end 41.91 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A07)) |
|
1542 |
(segment (start 41.91 99.06) (end 44.45 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A08)) |
|
1543 |
(segment (start 44.45 99.06) (end 46.99 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A09)) |
|
1544 |
(segment (start 46.99 99.06) (end 49.53 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0A)) |
|
1545 |
(segment (start 49.53 99.06) (end 52.07 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0B)) |
|
1546 |
(segment (start 52.07 99.06) (end 54.61 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0C)) |
|
1547 |
(segment (start 54.61 99.06) (end 58.42 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0D)) |
|
1548 |
(segment (start 58.42 99.06) (end 60.96 96.52) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0E)) |
|
1549 |
(segment (start 36.83 114.3) (end 36.83 110.49) (width 0.381) (layer B.Cu) (net 1)) |
|
1550 |
(segment (start 45.72 69.85) (end 48.26 69.85) (width 0.381) (layer B.Cu) (net 1)) |
|
1551 |
(segment (start 43.18 80.01) (end 43.18 74.93) (width 0.381) (layer B.Cu) (net 1)) |
|
1552 |
(segment (start 45.72 72.39) (end 45.72 69.85) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F28F4)) |
|
1553 |
(segment (start 43.18 74.93) (end 45.72 72.39) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F28F1)) |
|
1554 |
(segment (start 30.48 73.66) (end 30.48 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2533)) |
|
1555 |
(segment (start 27.94 76.2) (end 30.48 73.66) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2531)) |
|
1556 |
(segment (start 26.67 76.2) (end 27.94 76.2) (width 0.381) (layer B.Cu) (net 1)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1557 |
(segment (start 38.1 64.77) (end 38.1 63.5) (width 0.381) (layer B.Cu) (net 1)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1558 |
(segment (start 31.75 62.23) (end 30.48 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C911D)) |
1559 |
(segment (start 36.83 62.23) (end 31.75 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C911B)) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
1560 |
(segment (start 38.1 63.5) (end 36.83 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9118)) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1561 |
(segment (start 30.48 57.15) (end 31.75 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9124)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1562 |
(segment (start 29.21 58.42) (end 30.48 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9122)) |
1563 |
(segment (start 29.21 60.96) (end 29.21 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9121)) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
1564 |
(segment (start 30.48 62.23) (end 29.21 60.96) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9120)) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1565 |
(segment (start 36.83 119.38) (end 36.83 114.3) (width 0.381) (layer B.Cu) (net 1)) |
1566 |
(segment (start 26.67 76.2) (end 26.67 73.66) (width 0.381) (layer B.Cu) (net 1)) |
|
1567 |
(segment (start 68.58 72.39) (end 67.31 72.39) (width 0.381) (layer B.Cu) (net 1)) |
|
1568 |
(segment (start 71.12 62.23) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8008)) |
|
1569 |
(segment (start 71.12 64.77) (end 71.12 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8003)) |
|
1570 |
(segment (start 69.85 66.04) (end 71.12 64.77) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8002)) |
|
1571 |
(segment (start 67.31 66.04) (end 69.85 66.04) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8000)) |
|
1572 |
(segment (start 66.04 67.31) (end 67.31 66.04) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFF)) |
|
1573 |
(segment (start 66.04 71.12) (end 66.04 67.31) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFD)) |
|
1574 |
(segment (start 67.31 72.39) (end 66.04 71.12) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFB)) |
|
1575 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C800F)) |
|
1576 |
(segment (start 69.85 57.15) (end 71.12 57.15) (width 0.381) (layer B.Cu) (net 1)) |
|
1577 |
(segment (start 71.12 57.15) (end 72.39 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E0D)) |
|
1578 |
(segment (start 72.39 58.42) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E11)) |
|
1579 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E13)) |
|
1580 |
(segment (start 69.85 49.53) (end 71.12 49.53) (width 0.381) (layer B.Cu) (net 1)) |
|
1581 |
(segment (start 71.12 49.53) (end 72.39 50.8) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7DF5)) |
|
1582 |
(segment (start 72.39 50.8) (end 72.39 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E03)) |
|
1583 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E09)) |
|
1584 |
(segment (start 72.39 58.42) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E08)) |
|
1585 |
(segment (start 31.75 57.15) (end 39.37 57.15) (width 0.381) (layer B.Cu) (net 1)) |
|
1586 |
(segment (start 39.37 57.15) (end 46.99 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A99)) |
|
1587 |
(segment (start 46.99 57.15) (end 54.61 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9B)) |
|
1588 |
(segment (start 54.61 57.15) (end 62.23 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9C)) |
|
1589 |
(segment (start 62.23 57.15) (end 69.85 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9E)) |
|
1590 |
(segment (start 31.75 49.53) (end 39.37 49.53) (width 0.381) (layer B.Cu) (net 1)) |
|
1591 |
(segment (start 39.37 49.53) (end 46.99 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79E6)) |
|
1592 |
(segment (start 46.99 49.53) (end 54.61 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79E8)) |
|
1593 |
(segment (start 54.61 49.53) (end 62.23 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79EB)) |
|
1594 |
(segment (start 62.23 49.53) (end 69.85 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79EC)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1595 |
(segment (start 31.75 76.2) (end 40.64 67.31) (width 0.381) (layer B.Cu) (net 2)) |
1596 |
(segment (start 43.18 64.77) (end 40.64 67.31) (width 0.381) (layer B.Cu) (net 2)) |
|
1597 |
(segment (start 31.75 76.2) (end 29.21 78.74) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2524)) |
|
1598 |
(segment (start 29.21 78.74) (end 26.67 78.74) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F252A)) |
|
1599 |
(segment (start 63.5 88.9) (end 63.5 87.63) (width 0.381) (layer B.Cu) (net 2)) |
|
1600 |
(segment (start 62.23 86.36) (end 31.75 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EBF)) |
|
1601 |
(segment (start 63.5 87.63) (end 62.23 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EBE)) |
|
1602 |
(segment (start 63.5 96.52) (end 63.5 93.98) (width 0.381) (layer B.Cu) (net 2)) |
|
1603 |
(segment (start 63.5 93.98) (end 63.5 91.44) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA9)) |
|
1604 |
(segment (start 63.5 91.44) (end 63.5 88.9) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BAA)) |
|
1605 |
(segment (start 64.77 111.76) (end 64.77 106.68) (width 0.381) (layer B.Cu) (net 2)) |
|
1606 |
(segment (start 63.5 105.41) (end 63.5 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA5)) |
|
1607 |
(segment (start 64.77 106.68) (end 63.5 105.41) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA0)) |
|
1608 |
(segment (start 39.37 114.3) (end 41.91 114.3) (width 0.381) (layer B.Cu) (net 2)) |
|
1609 |
(segment (start 64.77 111.76) (end 67.31 111.76) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B6A)) |
|
1610 |
(segment (start 63.5 113.03) (end 64.77 111.76) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B69)) |
|
1611 |
(segment (start 43.18 113.03) (end 63.5 113.03) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B68)) |
|
1612 |
(segment (start 41.91 114.3) (end 43.18 113.03) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B67)) |
|
1613 |
(segment (start 34.29 96.52) (end 36.83 96.52) (width 0.381) (layer B.Cu) (net 2)) |
|
1614 |
(segment (start 36.83 96.52) (end 39.37 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293C)) |
|
1615 |
(segment (start 39.37 96.52) (end 41.91 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293D)) |
|
1616 |
(segment (start 41.91 96.52) (end 44.45 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293E)) |
|
1617 |
(segment (start 44.45 96.52) (end 46.99 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293F)) |
|
1618 |
(segment (start 46.99 96.52) (end 49.53 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2940)) |
|
1619 |
(segment (start 49.53 96.52) (end 52.07 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2941)) |
|
1620 |
(segment (start 52.07 96.52) (end 54.61 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2942)) |
|
1621 |
(segment (start 26.67 78.74) (end 26.67 80.01) (width 0.381) (layer B.Cu) (net 2)) |
|
1622 |
(segment (start 31.75 85.09) (end 31.75 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2931)) |
|
1623 |
(segment (start 26.67 80.01) (end 31.75 85.09) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F291D)) |
|
1624 |
(segment (start 31.75 93.98) (end 34.29 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2938)) |
|
1625 |
(segment (start 31.75 86.36) (end 31.75 93.98) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EC2)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1626 |
(segment (start 43.18 64.77) (end 43.18 63.5) (width 0.381) (layer B.Cu) (net 2)) |
1627 |
(segment (start 43.18 63.5) (end 44.45 62.23) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8474)) |
|
1628 |
(segment (start 44.45 62.23) (end 45.72 62.23) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8476)) |
|
1629 |
(segment (start 46.99 60.96) (end 46.99 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8479)) |
|
1630 |
(segment (start 45.72 62.23) (end 46.99 60.96) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8478)) |
|
1631 |
(segment (start 68.58 64.77) (end 68.58 62.23) (width 0.381) (layer B.Cu) (net 2)) |
|
1632 |
(segment (start 69.85 60.96) (end 69.85 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7FF8)) |
|
1633 |
(segment (start 68.58 62.23) (end 69.85 60.96) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7FF7)) |
|
1634 |
(segment (start 31.75 59.69) (end 39.37 59.69) (width 0.381) (layer B.Cu) (net 2)) |
|
1635 |
(segment (start 39.37 59.69) (end 46.99 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA5)) |
|
1636 |
(segment (start 46.99 59.69) (end 54.61 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA6)) |
|
1637 |
(segment (start 54.61 59.69) (end 62.23 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA7)) |
|
1638 |
(segment (start 62.23 59.69) (end 69.85 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA8)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1639 |
(segment (start 50.8 80.01) (end 50.8 78.74) (width 0.381) (layer B.Cu) (net 3)) |
1640 |
(segment (start 69.85 92.71) (end 66.04 96.52) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F29A7)) |
|
1641 |
(segment (start 69.85 80.01) (end 69.85 92.71) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F29A1)) |
|
1642 |
(segment (start 64.77 74.93) (end 69.85 80.01) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F299C)) |
|
1643 |
(segment (start 54.61 74.93) (end 64.77 74.93) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F299A)) |
|
1644 |
(segment (start 50.8 78.74) (end 54.61 74.93) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F2999)) |
|
1645 |
(segment (start 48.26 77.47) (end 48.26 80.01) (width 0.381) (layer B.Cu) (net 4)) |
|
1646 |
(segment (start 49.53 83.82) (end 49.53 82.55) (width 0.381) (layer B.Cu) (net 4)) |
|
1647 |
(segment (start 48.26 81.28) (end 48.26 80.01) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28EB)) |
|
1648 |
(segment (start 49.53 82.55) (end 48.26 81.28) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E7)) |
|
1649 |
(segment (start 44.45 83.82) (end 46.99 83.82) (width 0.381) (layer B.Cu) (net 4)) |
|
1650 |
(segment (start 46.99 83.82) (end 49.53 83.82) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E1)) |
|
1651 |
(segment (start 49.53 83.82) (end 52.07 83.82) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E3)) |
|
1652 |
(segment (start 52.07 91.44) (end 52.07 93.98) (width 0.381) (layer B.Cu) (net 5)) |
|
1653 |
(segment (start 49.53 91.44) (end 49.53 93.98) (width 0.381) (layer B.Cu) (net 6)) |
|
1654 |
(segment (start 53.34 80.01) (end 53.34 78.74) (width 0.381) (layer B.Cu) (net 7)) |
|
1655 |
(segment (start 68.58 91.44) (end 66.04 93.98) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F298F)) |
|
1656 |
(segment (start 68.58 80.01) (end 68.58 91.44) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F298C)) |
|
1657 |
(segment (start 64.77 76.2) (end 68.58 80.01) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2989)) |
|
1658 |
(segment (start 55.88 76.2) (end 64.77 76.2) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2987)) |
|
1659 |
(segment (start 53.34 78.74) (end 55.88 76.2) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2986)) |
|
1660 |
(segment (start 46.99 91.44) (end 46.99 93.98) (width 0.381) (layer B.Cu) (net 8)) |
|
1661 |
(segment (start 44.45 91.44) (end 44.45 93.98) (width 0.381) (layer B.Cu) (net 9)) |
|
1662 |
(segment (start 39.37 91.44) (end 39.37 93.98) (width 0.381) (layer B.Cu) (net 10)) |
|
1663 |
(segment (start 36.83 91.44) (end 36.83 93.98) (width 0.381) (layer B.Cu) (net 11)) |
|
1664 |
(segment (start 45.72 77.47) (end 45.72 80.01) (width 0.381) (layer B.Cu) (net 12)) |
|
1665 |
(segment (start 34.29 83.82) (end 36.83 83.82) (width 0.381) (layer B.Cu) (net 12)) |
|
1666 |
(segment (start 36.83 83.82) (end 39.37 83.82) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28D8)) |
|
1667 |
(segment (start 39.37 83.82) (end 41.91 83.82) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28D9)) |
|
1668 |
(segment (start 41.91 83.82) (end 45.72 80.01) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28DA)) |
|
1669 |
(segment (start 41.91 91.44) (end 41.91 93.98) (width 0.381) (layer B.Cu) (net 13)) |
|
1670 |
(segment (start 34.29 91.44) (end 34.29 93.98) (width 0.381) (layer B.Cu) (net 14)) |
|
1671 |
(segment (start 55.88 80.01) (end 55.88 78.74) (width 0.381) (layer B.Cu) (net 15)) |
|
1672 |
(segment (start 67.31 90.17) (end 66.04 91.44) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F2982)) |
|
1673 |
(segment (start 67.31 80.01) (end 67.31 90.17) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297F)) |
|
1674 |
(segment (start 64.77 77.47) (end 67.31 80.01) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297B)) |
|
1675 |
(segment (start 57.15 77.47) (end 64.77 77.47) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297A)) |
|
1676 |
(segment (start 55.88 78.74) (end 57.15 77.47) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F2979)) |
|
1677 |
(segment (start 73.66 91.44) (end 73.66 92.71) (width 0.381) (layer B.Cu) (net 16)) |
|
1678 |
(segment (start 35.56 74.93) (end 43.18 67.31) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EAE)) |
|
1679 |
(segment (start 43.18 67.31) (end 50.8 67.31) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EAF)) |
|
1680 |
(segment (start 50.8 67.31) (end 54.61 71.12) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB0)) |
|
1681 |
(segment (start 54.61 71.12) (end 64.77 71.12) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB2)) |
|
1682 |
(segment (start 64.77 71.12) (end 73.66 80.01) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB4)) |
|
1683 |
(segment (start 73.66 80.01) (end 73.66 91.44) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB6)) |
|
1684 |
(segment (start 72.39 93.98) (end 72.39 113.03) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB9)) |
|
1685 |
(segment (start 72.39 113.03) (end 73.66 114.3) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EBA)) |
|
1686 |
(segment (start 74.93 114.3) (end 73.66 114.3) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EBB)) |
|
1687 |
(segment (start 35.56 74.93) (end 35.56 80.01) (width 0.381) (layer B.Cu) (net 16)) |
|
1688 |
(segment (start 73.66 92.71) (end 72.39 93.98) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F3272)) |
|
1689 |
(segment (start 58.42 80.01) (end 59.69 78.74) (width 0.381) (layer B.Cu) (net 17)) |
|
1690 |
(segment (start 66.04 80.01) (end 66.04 88.9) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2976)) |
|
1691 |
(segment (start 64.77 78.74) (end 66.04 80.01) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2975)) |
|
1692 |
(segment (start 59.69 78.74) (end 64.77 78.74) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2974)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1693 |
(segment (start 68.58 67.31) (end 69.85 67.31) (width 0.381) (layer B.Cu) (net 18)) |
1694 |
(segment (start 73.66 62.23) (end 74.93 62.23) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8017)) |
|
1695 |
(segment (start 72.39 63.5) (end 73.66 62.23) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8015)) |
|
1696 |
(segment (start 72.39 64.77) (end 72.39 63.5) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8013)) |
|
1697 |
(segment (start 69.85 67.31) (end 72.39 64.77) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8012)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1698 |
(segment (start 38.1 80.01) (end 38.1 74.93) (width 0.381) (layer B.Cu) (net 19)) |
1699 |
(segment (start 76.2 111.76) (end 74.93 111.76) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EAB)) |
|
1700 |
(segment (start 77.47 113.03) (end 76.2 111.76) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EAA)) |
|
1701 |
(segment (start 77.47 114.3) (end 77.47 113.03) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA9)) |
|
1702 |
(segment (start 76.2 115.57) (end 77.47 114.3) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA8)) |
|
1703 |
(segment (start 72.39 115.57) (end 76.2 115.57) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA7)) |
|
1704 |
(segment (start 71.12 114.3) (end 72.39 115.57) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA6)) |
|
1705 |
(segment (start 71.12 93.98) (end 71.12 114.3) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA5)) |
|
1706 |
(segment (start 72.39 92.71) (end 71.12 93.98) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA4)) |
|
1707 |
(segment (start 72.39 80.01) (end 72.39 92.71) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA2)) |
|
1708 |
(segment (start 64.77 72.39) (end 72.39 80.01) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA0)) |
|
1709 |
(segment (start 53.34 72.39) (end 64.77 72.39) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9E)) |
|
1710 |
(segment (start 49.53 68.58) (end 53.34 72.39) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9C)) |
|
1711 |
(segment (start 44.45 68.58) (end 49.53 68.58) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9A)) |
|
1712 |
(segment (start 38.1 74.93) (end 44.45 68.58) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E98)) |
|
1713 |
(segment (start 67.31 114.3) (end 69.85 114.3) (width 0.381) (layer B.Cu) (net 20)) |
|
1714 |
(segment (start 72.39 116.84) (end 74.93 116.84) (width 0.381) (layer B.Cu) (net 20) (tstamp 534F2BC1)) |
|
1715 |
(segment (start 69.85 114.3) (end 72.39 116.84) (width 0.381) (layer B.Cu) (net 20) (tstamp 534F2BC0)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1716 |
(segment (start 68.58 69.85) (end 69.85 69.85) (width 0.381) (layer B.Cu) (net 21)) |
1717 |
(segment (start 69.85 69.85) (end 74.93 64.77) (width 0.381) (layer B.Cu) (net 21) (tstamp 534C801B)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1718 |
(segment (start 67.31 116.84) (end 69.85 116.84) (width 0.381) (layer B.Cu) (net 22)) |
1719 |
(segment (start 72.39 119.38) (end 74.93 119.38) (width 0.381) (layer B.Cu) (net 22) (tstamp 534F2BBC)) |
|
1720 |
(segment (start 69.85 116.84) (end 72.39 119.38) (width 0.381) (layer B.Cu) (net 22) (tstamp 534F2BB8)) |
|
1721 |
(segment (start 25.4 72.39) (end 24.13 73.66) (width 0.381) (layer B.Cu) (net 23)) |
|
1722 |
(segment (start 29.21 109.22) (end 29.21 106.68) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C844E)) |
|
1723 |
(segment (start 29.21 106.68) (end 29.21 105.41) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C844F)) |
|
1724 |
(segment (start 29.21 105.41) (end 27.94 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8450)) |
|
1725 |
(segment (start 27.94 104.14) (end 25.4 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8451)) |
|
1726 |
(segment (start 25.4 72.39) (end 27.94 72.39) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8455)) |
|
1727 |
(segment (start 27.94 72.39) (end 29.21 71.12) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8456)) |
|
1728 |
(segment (start 29.21 71.12) (end 29.21 64.77) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8458)) |
|
1729 |
(segment (start 29.21 64.77) (end 27.94 63.5) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8459)) |
|
1730 |
(segment (start 27.94 63.5) (end 27.94 53.34) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845A)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1731 |
(segment (start 27.94 53.34) (end 29.21 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845B)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1732 |
(segment (start 31.75 52.07) (end 29.21 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845C)) |
1733 |
(segment (start 29.21 109.22) (end 34.29 114.3) (width 0.381) (layer B.Cu) (net 23)) |
|
1734 |
(segment (start 24.13 102.87) (end 25.4 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1D)) |
|
1735 |
(segment (start 24.13 85.09) (end 24.13 102.87) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1C)) |
|
1736 |
(segment (start 22.86 83.82) (end 24.13 85.09) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1B)) |
|
1737 |
(segment (start 22.86 77.47) (end 22.86 83.82) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1A)) |
|
1738 |
(segment (start 24.13 76.2) (end 22.86 77.47) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F19)) |
|
1739 |
(segment (start 24.13 74.93) (end 24.13 76.2) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F18)) |
|
1740 |
(segment (start 24.13 73.66) (end 24.13 74.93) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F17)) |
|
1741 |
(segment (start 34.29 114.3) (end 34.29 110.49) (width 0.381) (layer B.Cu) (net 23)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1742 |
(segment (start 31.75 52.07) (end 39.37 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845D)) |
1743 |
(segment (start 39.37 52.07) (end 46.99 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845E)) |
|
1744 |
(segment (start 46.99 52.07) (end 54.61 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845F)) |
|
1745 |
(segment (start 54.61 52.07) (end 62.23 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8460)) |
|
1746 |
(segment (start 62.23 52.07) (end 69.85 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8461)) |
|
1747 |
(segment (start 34.29 119.38) (end 34.29 114.3) (width 0.381) (layer B.Cu) (net 23)) |
|
1748 |
(segment (start 31.75 52.07) (end 39.37 52.07) (width 0.381) (layer B.Cu) (net 23)) |
|
1749 |
(segment (start 39.37 52.07) (end 46.99 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FC)) |
|
1750 |
(segment (start 46.99 52.07) (end 54.61 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FD)) |
|
1751 |
(segment (start 54.61 52.07) (end 62.23 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FE)) |
|
1752 |
(segment (start 62.23 52.07) (end 69.85 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FF)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1753 |
(segment (start 34.29 102.87) (end 30.48 99.06) (width 0.381) (layer B.Cu) (net 24)) |
1754 |
(segment (start 27.94 83.82) (end 26.67 83.82) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A6F)) |
|
1755 |
(segment (start 30.48 86.36) (end 27.94 83.82) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A6C)) |
|
1756 |
(segment (start 30.48 99.06) (end 30.48 86.36) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A68)) |
|
1757 |
(segment (start 34.29 102.87) (end 36.83 102.87) (width 0.381) (layer B.Cu) (net 24)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1758 |
(segment (start 74.93 57.15) (end 74.93 48.26) (width 0.381) (layer B.Cu) (net 25)) |
1759 |
(segment (start 25.4 71.12) (end 26.67 71.12) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A6F)) |
|
1760 |
(segment (start 24.13 69.85) (end 25.4 71.12) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A6E)) |
|
1761 |
(segment (start 24.13 63.5) (end 24.13 69.85) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A64)) |
|
1762 |
(segment (start 26.67 60.96) (end 24.13 63.5) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A62)) |
|
1763 |
(segment (start 26.67 48.26) (end 26.67 60.96) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A5A)) |
|
1764 |
(segment (start 27.94 46.99) (end 26.67 48.26) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A57)) |
|
1765 |
(segment (start 73.66 46.99) (end 27.94 46.99) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A56)) |
|
1766 |
(segment (start 74.93 48.26) (end 73.66 46.99) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A54)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1767 |
|
1768 |
) |