bzr branch
http://bzr.ed.am/elec/quadcopter
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
1 |
(kicad_pcb (version 4) (host pcbnew 4.0.2-stable) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
2 |
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3 |
(general |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
4 |
(links 98) |
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50
by dan
finnished connecting all of the components together #=O) |
5 |
(no_connects 0) |
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
6 |
(area 22.415499 45.390999 77.914502 126.059001) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
7 |
(thickness 1.6) |
8 |
(drawings 0) |
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50
by dan
finnished connecting all of the components together #=O) |
9 |
(tracks 261) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
10 |
(zones 0) |
11 |
(modules 33) |
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12 |
(nets 26) |
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13 |
) |
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14 |
||
15 |
(page A3) |
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16 |
(layers |
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
17 |
(0 F.Cu signal) |
18 |
(31 B.Cu signal) |
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19 |
(32 B.Adhes user) |
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20 |
(33 F.Adhes user) |
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21 |
(34 B.Paste user) |
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22 |
(35 F.Paste user) |
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23 |
(36 B.SilkS user) |
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24 |
(37 F.SilkS user hide) |
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25 |
(38 B.Mask user) |
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26 |
(39 F.Mask user) |
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27 |
(40 Dwgs.User user) |
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28 |
(41 Cmts.User user) |
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29 |
(42 Eco1.User user) |
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30 |
(43 Eco2.User user) |
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31 |
(44 Edge.Cuts user) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
32 |
) |
33 |
||
34 |
(setup |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
35 |
(last_trace_width 0.381) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
36 |
(trace_clearance 0.254) |
37 |
(zone_clearance 0.508) |
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38 |
(zone_45_only no) |
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39 |
(trace_min 0.254) |
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40 |
(segment_width 0.2) |
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41 |
(edge_width 0.15) |
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42 |
(via_size 0.889) |
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43 |
(via_drill 0.635) |
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44 |
(via_min_size 0.889) |
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45 |
(via_min_drill 0.508) |
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46 |
(uvia_size 0.508) |
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47 |
(uvia_drill 0.127) |
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48 |
(uvias_allowed no) |
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49 |
(uvia_min_size 0.508) |
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50 |
(uvia_min_drill 0.127) |
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51 |
(pcb_text_width 0.3) |
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52 |
(pcb_text_size 1.5 1.5) |
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53 |
(mod_edge_width 0.15) |
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54 |
(mod_text_size 1.5 1.5) |
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55 |
(mod_text_width 0.15) |
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50
by dan
finnished connecting all of the components together #=O) |
56 |
(pad_size 1.524 2.032) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
57 |
(pad_drill 1.143) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
58 |
(pad_to_mask_clearance 0.2) |
59 |
(aux_axis_origin 0 0) |
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
60 |
(visible_elements FFFF7FBF) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
61 |
(pcbplotparams |
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
62 |
(layerselection 0x00030_80000001) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
63 |
(usegerberextensions true) |
64 |
(excludeedgelayer true) |
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65 |
(linewidth 0.100000) |
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66 |
(plotframeref false) |
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67 |
(viasonmask false) |
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68 |
(mode 1) |
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69 |
(useauxorigin false) |
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70 |
(hpglpennumber 1) |
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71 |
(hpglpenspeed 20) |
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72 |
(hpglpendiameter 15) |
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73 |
(hpglpenoverlay 2) |
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74 |
(psnegative false) |
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75 |
(psa4output false) |
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76 |
(plotreference true) |
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77 |
(plotvalue true) |
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78 |
(plotinvisibletext false) |
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79 |
(padsonsilk false) |
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80 |
(subtractmaskfromsilk false) |
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81 |
(outputformat 1) |
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82 |
(mirror false) |
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83 |
(drillshape 1) |
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84 |
(scaleselection 1) |
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85 |
(outputdirectory "")) |
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86 |
) |
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87 |
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88 |
(net 0 "") |
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89 |
(net 1 /GND) |
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90 |
(net 2 /VCC) |
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91 |
(net 3 N-000001) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
92 |
(net 4 N-0000017) |
93 |
(net 5 N-0000018) |
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94 |
(net 6 N-0000019) |
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95 |
(net 7 N-000002) |
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96 |
(net 8 N-0000020) |
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97 |
(net 9 N-0000021) |
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98 |
(net 10 N-0000022) |
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99 |
(net 11 N-0000023) |
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100 |
(net 12 N-0000024) |
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101 |
(net 13 N-0000025) |
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102 |
(net 14 N-0000026) |
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103 |
(net 15 N-000003) |
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104 |
(net 16 N-0000034) |
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105 |
(net 17 N-000004) |
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106 |
(net 18 N-0000048) |
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107 |
(net 19 N-000005) |
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108 |
(net 20 N-0000050) |
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109 |
(net 21 N-0000052) |
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110 |
(net 22 N-0000054) |
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111 |
(net 23 N-0000060) |
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112 |
(net 24 N-0000079) |
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113 |
(net 25 N-0000080) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
114 |
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115 |
(net_class Default "This is the default net class." |
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116 |
(clearance 0.254) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
117 |
(trace_width 0.381) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
118 |
(via_dia 0.889) |
119 |
(via_drill 0.635) |
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120 |
(uvia_dia 0.508) |
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121 |
(uvia_drill 0.127) |
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122 |
(add_net /GND) |
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123 |
(add_net /VCC) |
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124 |
(add_net N-000001) |
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125 |
(add_net N-0000017) |
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126 |
(add_net N-0000018) |
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127 |
(add_net N-0000019) |
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128 |
(add_net N-000002) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
129 |
(add_net N-0000020) |
130 |
(add_net N-0000021) |
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131 |
(add_net N-0000022) |
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132 |
(add_net N-0000023) |
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133 |
(add_net N-0000024) |
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134 |
(add_net N-0000025) |
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135 |
(add_net N-0000026) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
136 |
(add_net N-000003) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
137 |
(add_net N-0000034) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
138 |
(add_net N-000004) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
139 |
(add_net N-0000048) |
140 |
(add_net N-000005) |
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141 |
(add_net N-0000050) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
142 |
(add_net N-0000052) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
143 |
(add_net N-0000054) |
144 |
(add_net N-0000060) |
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145 |
(add_net N-0000079) |
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146 |
(add_net N-0000080) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
147 |
) |
148 |
||
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
149 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C7A7) |
150 |
(at 31.75 50.8 90) |
|
151 |
(path /53212777) |
|
152 |
(attr virtual) |
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153 |
(fp_text reference P4 (at -1.905 -3.81 90) (layer F.SilkS) |
|
154 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
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155 |
) |
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156 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
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157 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
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158 |
) |
|
159 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
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160 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
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161 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
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162 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
163 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
164 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
165 |
(net 23 N-0000060)) |
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166 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
167 |
(net 1 /GND)) |
|
168 |
) |
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169 |
||
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
170 |
(module R3 (layer F.Cu) (tedit 534C7795) (tstamp 5345C6FF) |
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50
by dan
finnished connecting all of the components together #=O) |
171 |
(at 34.29 106.68 90) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
172 |
(descr "Resitance 3 pas") |
173 |
(tags R) |
|
174 |
(path /5320CEF3) |
|
175 |
(autoplace_cost180 10) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
176 |
(fp_text reference R1 (at 0 0.127 90) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
177 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
178 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
179 |
(fp_text value 20K (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
180 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
181 |
) |
|
182 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
183 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
184 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
185 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
186 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
187 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
188 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
189 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
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59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
190 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
191 |
(net 23 N-0000060)) |
|
192 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
193 |
(net 24 N-0000079)) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
194 |
(model discret/resistor.wrl |
195 |
(at (xyz 0 0 0)) |
|
196 |
(scale (xyz 0.3 0.3 0.3)) |
|
197 |
(rotate (xyz 0 0 0)) |
|
198 |
) |
|
199 |
) |
|
200 |
||
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
201 |
(module R3 (layer F.Cu) (tedit 534C956E) (tstamp 5345CB8B) |
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50
by dan
finnished connecting all of the components together #=O) |
202 |
(at 36.83 106.68 270) |
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46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
203 |
(descr "Resitance 3 pas") |
204 |
(tags R) |
|
205 |
(path /5320CF02) |
|
206 |
(autoplace_cost180 10) |
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47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
207 |
(fp_text reference R2 (at 0 0.127 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
208 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
209 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
210 |
(fp_text value 10K (at 0 0.127 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
211 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
212 |
) |
|
213 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
214 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
215 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
216 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
217 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
218 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
219 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
220 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
221 |
(pad 1 thru_hole circle (at -3.81 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
222 |
(net 24 N-0000079)) |
|
223 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
224 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
225 |
(model discret/resistor.wrl |
226 |
(at (xyz 0 0 0)) |
|
227 |
(scale (xyz 0.3 0.3 0.3)) |
|
228 |
(rotate (xyz 0 0 0)) |
|
229 |
) |
|
230 |
) |
|
231 |
||
232 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C718) |
|
233 |
(at 39.37 58.42 90) |
|
234 |
(path /5321281E) |
|
235 |
(attr virtual) |
|
236 |
(fp_text reference P5 (at -1.905 -3.81 90) (layer F.SilkS) |
|
237 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
238 |
) |
|
239 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
240 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
241 |
) |
|
242 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
243 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
244 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
245 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
246 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
247 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
248 |
(net 2 /VCC)) |
|
249 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
250 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
251 |
) |
252 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
253 |
(module PINHEAD1-2 (layer F.Cu) (tedit 534C790C) (tstamp 534C7AD5) |
254 |
(at 35.56 119.38 180) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
255 |
(path /53212E1B) |
256 |
(attr virtual) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
257 |
(fp_text reference P1 (at -1.905 -3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
258 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
259 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
260 |
(fp_text value CONN_2 (at 0 3.81 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
261 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
262 |
) |
|
263 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
264 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
265 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
266 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
267 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
268 |
(pad 1 thru_hole oval (at -1.27 0 180) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
269 |
(net 1 /GND)) |
|
270 |
(pad 2 thru_hole oval (at 1.27 0 180) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
271 |
(net 23 N-0000060)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
272 |
) |
273 |
||
274 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C739) |
|
275 |
(at 69.85 58.42 90) |
|
276 |
(path /532128A9) |
|
277 |
(attr virtual) |
|
278 |
(fp_text reference P13 (at -1.905 -3.81 90) (layer F.SilkS) |
|
279 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
280 |
) |
|
281 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
282 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
283 |
) |
|
284 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
285 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
286 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
287 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
288 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
289 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
290 |
(net 2 /VCC)) |
|
291 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
292 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
293 |
) |
294 |
||
295 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C744) |
|
296 |
(at 62.23 58.42 90) |
|
297 |
(path /5321289A) |
|
298 |
(attr virtual) |
|
299 |
(fp_text reference P11 (at -1.905 -3.81 90) (layer F.SilkS) |
|
300 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
301 |
) |
|
302 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
303 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
304 |
) |
|
305 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
306 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
307 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
308 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
309 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
310 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
311 |
(net 2 /VCC)) |
|
312 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
313 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
314 |
) |
315 |
||
316 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C74F) |
|
317 |
(at 54.61 58.42 90) |
|
318 |
(path /5321288B) |
|
319 |
(attr virtual) |
|
320 |
(fp_text reference P9 (at -1.905 -3.81 90) (layer F.SilkS) |
|
321 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
322 |
) |
|
323 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
324 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
325 |
) |
|
326 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
327 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
328 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
329 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
330 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
331 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
332 |
(net 2 /VCC)) |
|
333 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
334 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
335 |
) |
336 |
||
337 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C75A) |
|
338 |
(at 46.99 58.42 90) |
|
339 |
(path /5321287C) |
|
340 |
(attr virtual) |
|
341 |
(fp_text reference P7 (at -1.905 -3.81 90) (layer F.SilkS) |
|
342 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
343 |
) |
|
344 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
345 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
346 |
) |
|
347 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
348 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
349 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
350 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
351 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
352 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
353 |
(net 2 /VCC)) |
|
354 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
355 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
356 |
) |
357 |
||
358 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C765) |
|
359 |
(at 31.75 58.42 90) |
|
360 |
(path /5321280F) |
|
361 |
(attr virtual) |
|
362 |
(fp_text reference P3 (at -1.905 -3.81 90) (layer F.SilkS) |
|
363 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
364 |
) |
|
365 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
366 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
367 |
) |
|
368 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
369 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
370 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
371 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
372 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
373 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
374 |
(net 2 /VCC)) |
|
375 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
376 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
377 |
) |
378 |
||
379 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C770) |
|
380 |
(at 69.85 50.8 90) |
|
381 |
(path /53212800) |
|
382 |
(attr virtual) |
|
383 |
(fp_text reference P14 (at -1.905 -3.81 90) (layer F.SilkS) |
|
384 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
385 |
) |
|
386 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
387 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
388 |
) |
|
389 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
390 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
391 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
392 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
393 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
394 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
395 |
(net 23 N-0000060)) |
|
396 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
397 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
398 |
) |
399 |
||
400 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C77B) |
|
401 |
(at 62.23 50.8 90) |
|
402 |
(path /532127F1) |
|
403 |
(attr virtual) |
|
404 |
(fp_text reference P12 (at -1.905 -3.81 90) (layer F.SilkS) |
|
405 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
406 |
) |
|
407 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
408 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
409 |
) |
|
410 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
411 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
412 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
413 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
414 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
415 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
416 |
(net 23 N-0000060)) |
|
417 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
418 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
419 |
) |
420 |
||
421 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C786) |
|
422 |
(at 54.61 50.8 90) |
|
423 |
(path /532127E2) |
|
424 |
(attr virtual) |
|
425 |
(fp_text reference P10 (at -1.905 -3.81 90) (layer F.SilkS) |
|
426 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
427 |
) |
|
428 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
429 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
430 |
) |
|
431 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
432 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
433 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
434 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
435 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
436 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
437 |
(net 23 N-0000060)) |
|
438 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
439 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
440 |
) |
441 |
||
442 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C791) |
|
443 |
(at 46.99 50.8 90) |
|
444 |
(path /532127D3) |
|
445 |
(attr virtual) |
|
446 |
(fp_text reference P8 (at -1.905 -3.81 90) (layer F.SilkS) |
|
447 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
448 |
) |
|
449 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
450 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
451 |
) |
|
452 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
453 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
454 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
455 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
456 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
457 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
458 |
(net 23 N-0000060)) |
|
459 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
460 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
461 |
) |
462 |
||
463 |
(module PINHEAD1-2 (layer F.Cu) (tedit 4C5EDFB2) (tstamp 5345C79C) |
|
464 |
(at 39.37 50.8 90) |
|
465 |
(path /532127B5) |
|
466 |
(attr virtual) |
|
467 |
(fp_text reference P6 (at -1.905 -3.81 90) (layer F.SilkS) |
|
468 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
469 |
) |
|
470 |
(fp_text value CONN_2 (at 0 3.81 90) (layer F.SilkS) |
|
471 |
(effects (font (size 1.016 1.016) (thickness 0.0889))) |
|
472 |
) |
|
473 |
(fp_line (start 2.54 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.254)) |
|
474 |
(fp_line (start 2.54 3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
475 |
(fp_line (start -2.54 -3.175) (end 2.54 -3.175) (layer F.SilkS) (width 0.254)) |
|
476 |
(fp_line (start -2.54 -3.175) (end -2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
477 |
(fp_line (start 2.54 -3.175) (end 2.54 3.175) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
478 |
(pad 1 thru_hole oval (at -1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
479 |
(net 23 N-0000060)) |
|
480 |
(pad 2 thru_hole oval (at 1.27 0 90) (size 1.524 2.286) (drill 1.143) (layers *.Cu F.Paste F.SilkS F.Mask) |
|
481 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
482 |
) |
483 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
484 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534C7F7E) (tstamp 534C7FE8) |
485 |
(at 68.58 68.58 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
486 |
(descr "Double rangee de contacts 2 x 5 pins") |
487 |
(tags CONN) |
|
488 |
(path /53497310) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
489 |
(fp_text reference P2 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
490 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
491 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
492 |
(fp_text value HC-SR04_PROXSENS (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
493 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
494 |
) |
|
495 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
496 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
497 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
498 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
499 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 1.524 2.286) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
500 |
(net 2 /VCC)) |
|
501 |
(pad 2 thru_hole oval (at -1.27 0 270) (size 1.524 2.286) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
502 |
(net 18 N-0000048)) |
|
503 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
504 |
(net 21 N-0000052)) |
|
505 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
506 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
507 |
(model pin_array\pins_array_4x1.wrl |
508 |
(at (xyz 0 0 0)) |
|
509 |
(scale (xyz 1 1 1)) |
|
510 |
(rotate (xyz 0 0 0)) |
|
511 |
) |
|
512 |
) |
|
513 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
514 |
(module IMU_Mount (layer F.Cu) (tedit 534F2E1F) (tstamp 534F1CEE) |
515 |
(at 55.88 114.3) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
516 |
(path /532A16AB) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
517 |
(fp_text reference U1 (at 0 -2.54) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
518 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
519 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
520 |
(fp_text value IMU_MOUNT (at 0 0) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
521 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
522 |
) |
|
523 |
(fp_line (start -12.7 8.89) (end 12.7 8.89) (layer F.SilkS) (width 0.15)) |
|
524 |
(fp_line (start -12.7 8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
525 |
(fp_line (start 12.7 8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
526 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
527 |
(fp_line (start -12.7 -8.89) (end 12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
528 |
(fp_line (start 12.7 -8.89) (end -12.7 -8.89) (layer F.SilkS) (width 0.15)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
529 |
(pad 1 thru_hole circle (at 11.43 2.54) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
530 |
(net 22 N-0000054)) |
|
531 |
(pad 2 thru_hole oval (at 11.43 0) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
532 |
(net 20 N-0000050)) |
|
533 |
(pad 3 thru_hole oval (at 11.43 -2.54) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
534 |
(net 2 /VCC)) |
|
535 |
(pad 4 thru_hole circle (at 11.43 -5.08) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
536 |
(net 1 /GND)) |
|
537 |
(pad 5 thru_hole circle (at -11.43 7.62) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
538 |
(pad 6 thru_hole circle (at -11.43 5.08) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
539 |
(pad 7 thru_hole oval (at -11.43 2.54) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
540 |
(pad 8 thru_hole oval (at -11.43 0) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
541 |
(pad 9 thru_hole oval (at -11.43 -2.54) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
542 |
(pad 10 thru_hole circle (at -11.43 -5.08) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
543 |
(pad 11 thru_hole circle (at -11.43 -7.62) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
544 |
) |
545 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
546 |
(module Arduino_Mega_Shield_Partial (layer F.Cu) (tedit 534F2CAF) (tstamp 534F2CD5) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
547 |
(at 49.53 77.47) |
548 |
(path /532A24F4) |
|
549 |
(fp_text reference U3 (at 0 -2.54) (layer F.SilkS) |
|
550 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
551 |
) |
|
552 |
(fp_text value ARDUINO_MEGA_SHIELD (at 0 0) (layer F.SilkS) |
|
553 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
|
554 |
) |
|
555 |
(fp_line (start 26.67 -31.75) (end 26.67 48.26) (layer F.SilkS) (width 0.15)) |
|
556 |
(fp_line (start -24.13 48.26) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
557 |
(fp_line (start 26.67 48.26) (end -24.13 48.26) (layer F.SilkS) (width 0.15)) |
|
558 |
(fp_line (start 26.67 -31.75) (end -24.13 -31.75) (layer F.SilkS) (width 0.15)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
559 |
(pad 1 thru_hole circle (at -22.86 -11.43) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
560 |
(pad 2 thru_hole circle (at -22.86 -8.89) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
561 |
(pad 3 thru_hole oval (at -22.86 -6.35) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
562 |
(net 25 N-0000080)) |
|
563 |
(pad 4 thru_hole oval (at -22.86 -3.81) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
564 |
(net 1 /GND)) |
|
565 |
(pad 5 thru_hole circle (at -22.86 -1.27) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
566 |
(net 1 /GND)) |
|
567 |
(pad 6 thru_hole circle (at -22.86 1.27) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
568 |
(net 2 /VCC)) |
|
569 |
(pad 7 thru_hole oval (at -22.86 6.35) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
570 |
(net 24 N-0000079)) |
|
571 |
(pad 8 thru_hole oval (at -22.86 8.89) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
572 |
(pad 9 thru_hole circle (at -22.86 11.43) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
573 |
(pad 10 thru_hole circle (at -22.86 13.97) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
574 |
(pad 11 thru_hole circle (at -22.86 16.51) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
575 |
(pad 12 thru_hole circle (at -22.86 19.05) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
576 |
(pad 13 thru_hole circle (at -22.86 21.59) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
577 |
(pad 14 thru_hole circle (at -22.86 24.13) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
578 |
(pad 15 thru_hole circle (at -22.86 29.21) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
579 |
(pad 16 thru_hole circle (at -22.86 31.75) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
580 |
(pad 17 thru_hole circle (at -22.86 34.29) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
581 |
(pad 18 thru_hole circle (at -22.86 36.83) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
582 |
(pad 19 thru_hole circle (at -22.86 39.37) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
583 |
(pad 20 thru_hole circle (at -22.86 41.91) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
584 |
(pad 21 thru_hole circle (at -22.86 44.45) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
585 |
(pad 23 thru_hole circle (at 25.4 41.91) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
586 |
(net 22 N-0000054)) |
|
587 |
(pad 24 thru_hole oval (at 25.4 39.37) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
588 |
(net 20 N-0000050)) |
|
589 |
(pad 25 thru_hole oval (at 25.4 36.83) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
590 |
(net 16 N-0000034)) |
|
591 |
(pad 26 thru_hole circle (at 25.4 34.29) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
592 |
(net 19 N-000005)) |
|
593 |
(pad 27 thru_hole circle (at 25.4 31.75) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
594 |
(pad 28 thru_hole circle (at 25.4 29.21) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
595 |
(pad 29 thru_hole circle (at 25.4 26.67) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
596 |
(pad 30 thru_hole circle (at 25.4 24.13) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
597 |
(pad 31 thru_hole circle (at 25.4 19.05) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
598 |
(pad 32 thru_hole circle (at 25.4 16.51) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
599 |
(pad 33 thru_hole oval (at 25.4 13.97) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
600 |
(pad 34 thru_hole oval (at 25.4 11.43) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
601 |
(pad 35 thru_hole oval (at 25.4 8.89) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
602 |
(pad 36 thru_hole oval (at 25.4 6.35) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
603 |
(pad 37 thru_hole oval (at 25.4 3.81) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
604 |
(pad 38 thru_hole circle (at 25.4 1.27) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
605 |
(pad 39 thru_hole circle (at 25.4 -2.54) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
606 |
(pad 40 thru_hole circle (at 25.4 -5.08) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
607 |
(pad 41 thru_hole circle (at 25.4 -7.62) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
608 |
(pad 42 thru_hole circle (at 25.4 -10.16) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
609 |
(pad 43 thru_hole circle (at 25.4 -12.7) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
610 |
(net 21 N-0000052)) |
|
611 |
(pad 44 thru_hole circle (at 25.4 -15.24) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
612 |
(net 18 N-0000048)) |
|
613 |
(pad 45 thru_hole circle (at 25.4 -17.78) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
614 |
(net 1 /GND)) |
|
615 |
(pad 46 thru_hole circle (at 25.4 -20.32) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
616 |
(net 25 N-0000080)) |
|
617 |
(pad 22 thru_hole circle (at -22.86 46.99) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
618 |
) |
619 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
620 |
(module R3 (layer F.Cu) (tedit 534F3037) (tstamp 534C80B7) |
621 |
(at 48.26 73.66 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
622 |
(descr "Resitance 3 pas") |
623 |
(tags R) |
|
624 |
(path /53496D70) |
|
625 |
(autoplace_cost180 10) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
626 |
(fp_text reference R3 (at 0 0.127 270) (layer F.SilkS) hide |
627 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
|
628 |
) |
|
629 |
(fp_text value 10k (at 0 0.127 270) (layer F.SilkS) |
|
630 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
|
631 |
) |
|
632 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
633 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
634 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
635 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
636 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
637 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
638 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
639 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
640 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
641 |
(net 1 /GND)) |
|
642 |
(pad 2 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
643 |
(net 4 N-0000017)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
644 |
(model discret/resistor.wrl |
645 |
(at (xyz 0 0 0)) |
|
646 |
(scale (xyz 0.3 0.3 0.3)) |
|
647 |
(rotate (xyz 0 0 0)) |
|
648 |
) |
|
649 |
) |
|
650 |
||
651 |
(module R3 (layer F.Cu) (tedit 534F3031) (tstamp 534F21B5) |
|
652 |
(at 45.72 73.66 90) |
|
653 |
(descr "Resitance 3 pas") |
|
654 |
(tags R) |
|
655 |
(path /53496D82) |
|
656 |
(autoplace_cost180 10) |
|
657 |
(fp_text reference R4 (at 0 0.127 90) (layer F.SilkS) hide |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
658 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
659 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
660 |
(fp_text value 10k (at 0 0.127 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
661 |
(effects (font (size 1.397 1.27) (thickness 0.2032))) |
662 |
) |
|
663 |
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.2032)) |
|
664 |
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
665 |
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
666 |
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.2032)) |
|
667 |
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
668 |
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.2032)) |
|
669 |
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.2032)) |
|
670 |
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.2032)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
671 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
672 |
(net 12 N-0000024)) |
|
673 |
(pad 2 thru_hole oval (at 3.81 0 90) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
674 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
675 |
(model discret/resistor.wrl |
676 |
(at (xyz 0 0 0)) |
|
677 |
(scale (xyz 0.3 0.3 0.3)) |
|
678 |
(rotate (xyz 0 0 0)) |
|
679 |
) |
|
680 |
) |
|
681 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
682 |
(module pin_array_4x2 (layer F.Cu) (tedit 534F3091) (tstamp 534C8C00) |
683 |
(at 62.23 92.71 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
684 |
(descr "Double rangee de contacts 2 x 4 pins") |
685 |
(tags CONN) |
|
686 |
(path /53496DB9) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
687 |
(fp_text reference P18 (at 0 -3.81 90) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
688 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
689 |
) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
690 |
(fp_text value "ESC P & G" (at 0 3.81 90) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
691 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
692 |
) |
|
693 |
(fp_line (start -5.08 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
694 |
(fp_line (start 5.08 -2.54) (end 5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
695 |
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.3048)) |
|
696 |
(fp_line (start -5.08 2.54) (end -5.08 -2.54) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
697 |
(pad 1 thru_hole circle (at -3.81 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
698 |
(net 2 /VCC)) |
|
699 |
(pad 2 thru_hole circle (at -3.81 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
700 |
(net 1 /GND)) |
|
701 |
(pad 3 thru_hole circle (at -1.27 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
702 |
(net 2 /VCC)) |
|
703 |
(pad 4 thru_hole circle (at -1.27 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
704 |
(net 1 /GND)) |
|
705 |
(pad 5 thru_hole circle (at 1.27 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
706 |
(net 2 /VCC)) |
|
707 |
(pad 6 thru_hole circle (at 1.27 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
708 |
(net 1 /GND)) |
|
709 |
(pad 7 thru_hole circle (at 3.81 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
710 |
(net 2 /VCC)) |
|
711 |
(pad 8 thru_hole circle (at 3.81 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
712 |
(net 1 /GND)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
713 |
(model pin_array/pins_array_4x2.wrl |
714 |
(at (xyz 0 0 0)) |
|
715 |
(scale (xyz 1 1 1)) |
|
716 |
(rotate (xyz 0 0 0)) |
|
717 |
) |
|
718 |
) |
|
719 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
720 |
(module PIN_ARRAY_4x1 (layer F.Cu) (tedit 534F3167) (tstamp 5349B010) |
721 |
(at 66.04 92.71 270) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
722 |
(descr "Double rangee de contacts 2 x 5 pins") |
723 |
(tags CONN) |
|
724 |
(path /53496DBF) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
725 |
(fp_text reference P17 (at 0 -2.54 270) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
726 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
727 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
728 |
(fp_text value "ESC Sig" (at 0 2.54 270) (layer F.SilkS) hide |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
729 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
730 |
) |
|
731 |
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
732 |
(fp_line (start 5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
733 |
(fp_line (start -5.08 -1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.254)) |
|
734 |
(fp_line (start 5.08 1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
735 |
(pad 1 thru_hole oval (at -3.81 0 270) (size 2.032 1.524) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
736 |
(net 17 N-000004)) |
|
737 |
(pad 2 thru_hole circle (at -1.27 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
738 |
(net 15 N-000003)) |
|
739 |
(pad 3 thru_hole circle (at 1.27 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
740 |
(net 7 N-000002)) |
|
741 |
(pad 4 thru_hole circle (at 3.81 0 270) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
742 |
(net 3 N-000001)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
743 |
(model pin_array\pins_array_4x1.wrl |
744 |
(at (xyz 0 0 0)) |
|
745 |
(scale (xyz 1 1 1)) |
|
746 |
(rotate (xyz 0 0 0)) |
|
747 |
) |
|
748 |
) |
|
749 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
750 |
(module D3 (layer F.Cu) (tedit 534F3058) (tstamp 534EE282) |
751 |
(at 34.29 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
752 |
(descr "Diode 3 pas") |
753 |
(tags "DIODE DEV") |
|
754 |
(path /53496D88) |
|
755 |
(fp_text reference D1 (at 0 0 90) (layer F.SilkS) |
|
756 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
757 |
) |
|
758 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
759 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
760 |
) |
|
761 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
762 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
763 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
764 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
765 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
766 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
767 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
768 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
769 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
770 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
771 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
772 |
(net 12 N-0000024)) |
|
773 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
774 |
(net 14 N-0000026)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
775 |
(model discret/diode.wrl |
776 |
(at (xyz 0 0 0)) |
|
777 |
(scale (xyz 0.3 0.3 0.3)) |
|
778 |
(rotate (xyz 0 0 0)) |
|
779 |
) |
|
780 |
) |
|
781 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
782 |
(module D3 (layer F.Cu) (tedit 534F3068) (tstamp 5349B03C) |
783 |
(at 41.91 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
784 |
(descr "Diode 3 pas") |
785 |
(tags "DIODE DEV") |
|
786 |
(path /53496D8E) |
|
787 |
(fp_text reference D4 (at 0 0 90) (layer F.SilkS) |
|
788 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
789 |
) |
|
790 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
791 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
792 |
) |
|
793 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
794 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
795 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
796 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
797 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
798 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
799 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
800 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
801 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
802 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
803 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
804 |
(net 12 N-0000024)) |
|
805 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
806 |
(net 13 N-0000025)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
807 |
(model discret/diode.wrl |
808 |
(at (xyz 0 0 0)) |
|
809 |
(scale (xyz 0.3 0.3 0.3)) |
|
810 |
(rotate (xyz 0 0 0)) |
|
811 |
) |
|
812 |
) |
|
813 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
814 |
(module D3 (layer F.Cu) (tedit 534F305E) (tstamp 5349B04C) |
815 |
(at 36.83 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
816 |
(descr "Diode 3 pas") |
817 |
(tags "DIODE DEV") |
|
818 |
(path /53496D94) |
|
819 |
(fp_text reference D2 (at 0 0 90) (layer F.SilkS) |
|
820 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
821 |
) |
|
822 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
823 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
824 |
) |
|
825 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
826 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
827 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
828 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
829 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
830 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
831 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
832 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
833 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
834 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
835 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
836 |
(net 12 N-0000024)) |
|
837 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
838 |
(net 11 N-0000023)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
839 |
(model discret/diode.wrl |
840 |
(at (xyz 0 0 0)) |
|
841 |
(scale (xyz 0.3 0.3 0.3)) |
|
842 |
(rotate (xyz 0 0 0)) |
|
843 |
) |
|
844 |
) |
|
845 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
846 |
(module D3 (layer F.Cu) (tedit 534F3063) (tstamp 5349B05C) |
847 |
(at 39.37 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
848 |
(descr "Diode 3 pas") |
849 |
(tags "DIODE DEV") |
|
850 |
(path /53496D9A) |
|
851 |
(fp_text reference D3 (at 0 0 90) (layer F.SilkS) |
|
852 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
853 |
) |
|
854 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
855 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
856 |
) |
|
857 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
858 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
859 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
860 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
861 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
862 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
863 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
864 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
865 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
866 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
867 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
868 |
(net 12 N-0000024)) |
|
869 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
870 |
(net 10 N-0000022)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
871 |
(model discret/diode.wrl |
872 |
(at (xyz 0 0 0)) |
|
873 |
(scale (xyz 0.3 0.3 0.3)) |
|
874 |
(rotate (xyz 0 0 0)) |
|
875 |
) |
|
876 |
) |
|
877 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
878 |
(module D3 (layer F.Cu) (tedit 534F306C) (tstamp 5349B06C) |
879 |
(at 44.45 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
880 |
(descr "Diode 3 pas") |
881 |
(tags "DIODE DEV") |
|
882 |
(path /53496DA0) |
|
883 |
(fp_text reference D5 (at 0 0 90) (layer F.SilkS) |
|
884 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
885 |
) |
|
886 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
887 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
888 |
) |
|
889 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
890 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
891 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
892 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
893 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
894 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
895 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
896 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
897 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
898 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
899 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
900 |
(net 4 N-0000017)) |
|
901 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
902 |
(net 9 N-0000021)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
903 |
(model discret/diode.wrl |
904 |
(at (xyz 0 0 0)) |
|
905 |
(scale (xyz 0.3 0.3 0.3)) |
|
906 |
(rotate (xyz 0 0 0)) |
|
907 |
) |
|
908 |
) |
|
909 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
910 |
(module D3 (layer F.Cu) (tedit 534C9281) (tstamp 5349B07C) |
|
50
by dan
finnished connecting all of the components together #=O) |
911 |
(at 46.99 87.63 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
912 |
(descr "Diode 3 pas") |
913 |
(tags "DIODE DEV") |
|
914 |
(path /53496DA6) |
|
915 |
(fp_text reference D6 (at 0 0 90) (layer F.SilkS) |
|
916 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
917 |
) |
|
918 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
919 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
920 |
) |
|
921 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
922 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
923 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
924 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
925 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
926 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
927 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
928 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
929 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
930 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
931 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
932 |
(net 4 N-0000017)) |
|
933 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
934 |
(net 8 N-0000020)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
935 |
(model discret/diode.wrl |
936 |
(at (xyz 0 0 0)) |
|
937 |
(scale (xyz 0.3 0.3 0.3)) |
|
938 |
(rotate (xyz 0 0 0)) |
|
939 |
) |
|
940 |
) |
|
941 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
942 |
(module D3 (layer F.Cu) (tedit 534F3072) (tstamp 5349B08C) |
943 |
(at 49.53 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
944 |
(descr "Diode 3 pas") |
945 |
(tags "DIODE DEV") |
|
946 |
(path /53496DAC) |
|
947 |
(fp_text reference D7 (at 0 0 90) (layer F.SilkS) |
|
948 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
949 |
) |
|
950 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
951 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
952 |
) |
|
953 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
954 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
955 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
956 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
957 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
958 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
959 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
960 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
961 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
962 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
963 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
964 |
(net 4 N-0000017)) |
|
965 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
966 |
(net 6 N-0000019)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
967 |
(model discret/diode.wrl |
968 |
(at (xyz 0 0 0)) |
|
969 |
(scale (xyz 0.3 0.3 0.3)) |
|
970 |
(rotate (xyz 0 0 0)) |
|
971 |
) |
|
972 |
) |
|
973 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
974 |
(module D3 (layer F.Cu) (tedit 534F3077) (tstamp 5349B09C) |
975 |
(at 52.07 87.63 90) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
976 |
(descr "Diode 3 pas") |
977 |
(tags "DIODE DEV") |
|
978 |
(path /53496DB2) |
|
979 |
(fp_text reference D8 (at 0 0 90) (layer F.SilkS) |
|
980 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
981 |
) |
|
982 |
(fp_text value DIODE (at 0 0 90) (layer F.SilkS) hide |
|
983 |
(effects (font (size 1.016 1.016) (thickness 0.2032))) |
|
984 |
) |
|
985 |
(fp_line (start 3.81 0) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
986 |
(fp_line (start 3.048 0) (end 3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
987 |
(fp_line (start 3.048 -1.016) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048)) |
|
988 |
(fp_line (start -3.048 -1.016) (end -3.048 0) (layer F.SilkS) (width 0.3048)) |
|
989 |
(fp_line (start -3.048 0) (end -3.81 0) (layer F.SilkS) (width 0.3048)) |
|
990 |
(fp_line (start -3.048 0) (end -3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
991 |
(fp_line (start -3.048 1.016) (end 3.048 1.016) (layer F.SilkS) (width 0.3048)) |
|
992 |
(fp_line (start 3.048 1.016) (end 3.048 0) (layer F.SilkS) (width 0.3048)) |
|
993 |
(fp_line (start 2.54 -1.016) (end 2.54 1.016) (layer F.SilkS) (width 0.3048)) |
|
994 |
(fp_line (start 2.286 1.016) (end 2.286 -1.016) (layer F.SilkS) (width 0.3048)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
995 |
(pad 2 thru_hole circle (at 3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
996 |
(net 4 N-0000017)) |
|
997 |
(pad 1 thru_hole circle (at -3.81 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
998 |
(net 5 N-0000018)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
999 |
(model discret/diode.wrl |
1000 |
(at (xyz 0 0 0)) |
|
1001 |
(scale (xyz 0.3 0.3 0.3)) |
|
1002 |
(rotate (xyz 0 0 0)) |
|
1003 |
) |
|
1004 |
) |
|
1005 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1006 |
(module Arduino_Mini_Pro_Mount (layer F.Cu) (tedit 534F322E) (tstamp 534F32C6) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1007 |
(at 49.53 71.12 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1008 |
(path /53497285) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1009 |
(fp_text reference U4 (at -1.27 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1010 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1011 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1012 |
(fp_text value ARDUINO_MINI_PRO_MOUNT (at 1.27 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1013 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1014 |
) |
|
1015 |
(fp_line (start -10.16 15.24) (end 7.62 15.24) (layer F.SilkS) (width 0.15)) |
|
1016 |
(fp_line (start 7.62 15.24) (end 7.62 -17.78) (layer F.SilkS) (width 0.15)) |
|
1017 |
(fp_line (start 7.62 -17.78) (end -10.16 -17.78) (layer F.SilkS) (width 0.15)) |
|
1018 |
(fp_line (start -10.16 -17.78) (end -10.16 15.24) (layer F.SilkS) (width 0.15)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
1019 |
(pad 1 thru_hole circle (at -8.89 -13.97 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
1020 |
(net 16 N-0000034)) |
|
1021 |
(pad 2 thru_hole circle (at -8.89 -11.43 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1022 |
(net 19 N-000005)) |
|
1023 |
(pad 3 thru_hole circle (at -8.89 -8.89 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1024 |
(pad 4 thru_hole circle (at -8.89 -6.35 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1025 |
(net 1 /GND)) |
|
1026 |
(pad 5 thru_hole circle (at -8.89 -3.81 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1027 |
(net 12 N-0000024)) |
|
1028 |
(pad 6 thru_hole circle (at -8.89 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1029 |
(net 4 N-0000017)) |
|
1030 |
(pad 7 thru_hole circle (at -8.89 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1031 |
(net 3 N-000001)) |
|
1032 |
(pad 8 thru_hole circle (at -8.89 3.81 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1033 |
(net 7 N-000002)) |
|
1034 |
(pad 9 thru_hole circle (at -8.89 6.35 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1035 |
(net 15 N-000003)) |
|
1036 |
(pad 10 thru_hole circle (at -8.89 8.89 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1037 |
(net 17 N-000004)) |
|
1038 |
(pad 11 thru_hole oval (at -8.89 11.43 90) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1039 |
(pad 12 thru_hole oval (at -8.89 13.97 90) (size 1.524 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1040 |
(pad 13 thru_hole circle (at 6.35 13.97 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1041 |
(pad 14 thru_hole circle (at 6.35 11.43 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1042 |
(pad 15 thru_hole circle (at 6.35 8.89 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1043 |
(pad 16 thru_hole circle (at 6.35 6.35 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1044 |
(pad 17 thru_hole circle (at 6.35 3.81 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1045 |
(pad 18 thru_hole circle (at 6.35 1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1046 |
(pad 19 thru_hole circle (at 6.35 -1.27 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1047 |
(pad 20 thru_hole circle (at 6.35 -3.81 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1048 |
(pad 21 thru_hole circle (at 6.35 -6.35 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1049 |
(net 2 /VCC)) |
|
1050 |
(pad 22 thru_hole circle (at 6.35 -8.89 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
1051 |
(pad 23 thru_hole circle (at 6.35 -11.43 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1052 |
(net 1 /GND)) |
|
1053 |
(pad 24 thru_hole circle (at 6.35 -13.97 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1054 |
) |
1055 |
||
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1056 |
(module 9x3_Conn_Block (layer F.Cu) (tedit 534C7723) (tstamp 534C9726) |
|
50
by dan
finnished connecting all of the components together #=O) |
1057 |
(at 44.45 96.52 90) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1058 |
(path /53497B7A) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1059 |
(fp_text reference U5 (at -5.08 0 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1060 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1061 |
) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1062 |
(fp_text value 9X3_CONN_BLOCK (at 5.08 -1.27 180) (layer F.SilkS) |
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1063 |
(effects (font (size 1.5 1.5) (thickness 0.15))) |
1064 |
) |
|
1065 |
(fp_line (start -3.81 -11.43) (end 3.81 -11.43) (layer F.SilkS) (width 0.15)) |
|
1066 |
(fp_line (start 3.81 -11.43) (end 3.81 11.43) (layer F.SilkS) (width 0.15)) |
|
1067 |
(fp_line (start 3.81 11.43) (end -3.81 11.43) (layer F.SilkS) (width 0.15)) |
|
1068 |
(fp_line (start -3.81 11.43) (end -3.81 -11.43) (layer F.SilkS) (width 0.15)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
1069 |
(pad 1 thru_hole circle (at -2.54 -10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
1070 |
(net 1 /GND)) |
|
1071 |
(pad 2 thru_hole circle (at -2.54 -7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1072 |
(net 1 /GND)) |
|
1073 |
(pad 3 thru_hole circle (at -2.54 -5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1074 |
(net 1 /GND)) |
|
1075 |
(pad 4 thru_hole circle (at -2.54 -2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1076 |
(net 1 /GND)) |
|
1077 |
(pad 5 thru_hole circle (at -2.54 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1078 |
(net 1 /GND)) |
|
1079 |
(pad 6 thru_hole circle (at -2.54 2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1080 |
(net 1 /GND)) |
|
1081 |
(pad 7 thru_hole circle (at -2.54 5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1082 |
(net 1 /GND)) |
|
1083 |
(pad 8 thru_hole circle (at -2.54 7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1084 |
(net 1 /GND)) |
|
1085 |
(pad 9 thru_hole circle (at -2.54 10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1086 |
(net 1 /GND)) |
|
1087 |
(pad 10 thru_hole circle (at 0 -10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1088 |
(net 2 /VCC)) |
|
1089 |
(pad 11 thru_hole circle (at 0 -7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1090 |
(net 2 /VCC)) |
|
1091 |
(pad 12 thru_hole circle (at 0 -5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1092 |
(net 2 /VCC)) |
|
1093 |
(pad 13 thru_hole circle (at 0 -2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1094 |
(net 2 /VCC)) |
|
1095 |
(pad 14 thru_hole circle (at 0 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1096 |
(net 2 /VCC)) |
|
1097 |
(pad 15 thru_hole circle (at 0 2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1098 |
(net 2 /VCC)) |
|
1099 |
(pad 16 thru_hole circle (at 0 5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1100 |
(net 2 /VCC)) |
|
1101 |
(pad 17 thru_hole circle (at 0 7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1102 |
(net 2 /VCC)) |
|
1103 |
(pad 18 thru_hole circle (at 0 10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1104 |
(net 2 /VCC)) |
|
1105 |
(pad 19 thru_hole circle (at 2.54 -10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1106 |
(net 14 N-0000026)) |
|
1107 |
(pad 20 thru_hole circle (at 2.54 -7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1108 |
(net 11 N-0000023)) |
|
1109 |
(pad 21 thru_hole circle (at 2.54 -5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1110 |
(net 10 N-0000022)) |
|
1111 |
(pad 22 thru_hole circle (at 2.54 -2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1112 |
(net 13 N-0000025)) |
|
1113 |
(pad 23 thru_hole circle (at 2.54 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1114 |
(net 9 N-0000021)) |
|
1115 |
(pad 24 thru_hole circle (at 2.54 2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1116 |
(net 8 N-0000020)) |
|
1117 |
(pad 25 thru_hole circle (at 2.54 5.08 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1118 |
(net 6 N-0000019)) |
|
1119 |
(pad 26 thru_hole circle (at 2.54 7.62 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1120 |
(net 5 N-0000018)) |
|
1121 |
(pad 27 thru_hole circle (at 2.54 10.16 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1122 |
) |
1123 |
||
1124 |
(module LM78XXV (layer F.Cu) (tedit 534C7888) (tstamp 5345C7C5) |
|
1125 |
(at 36.83 114.3 90) |
|
1126 |
(descr "Regulateur TO220 serie LM78xx") |
|
1127 |
(tags "TR TO220") |
|
1128 |
(path /5320D1B3) |
|
1129 |
(fp_text reference U2 (at 3.81 0 180) (layer F.SilkS) |
|
1130 |
(effects (font (size 1.524 1.016) (thickness 0.2032))) |
|
1131 |
) |
|
1132 |
(fp_text value 7805 (at -3.175 -0.635 180) (layer F.SilkS) |
|
1133 |
(effects (font (size 1.524 1.016) (thickness 0.2032))) |
|
1134 |
) |
|
1135 |
(fp_line (start 1.905 -4.445) (end 2.54 -4.445) (layer F.SilkS) (width 0.254)) |
|
1136 |
(fp_line (start 2.54 -4.445) (end 2.54 4.445) (layer F.SilkS) (width 0.254)) |
|
1137 |
(fp_line (start 2.54 4.445) (end 1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1138 |
(fp_line (start -1.905 -4.445) (end 1.905 -4.445) (layer F.SilkS) (width 0.254)) |
|
1139 |
(fp_line (start 1.905 -4.445) (end 1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1140 |
(fp_line (start 1.905 4.445) (end -1.905 4.445) (layer F.SilkS) (width 0.254)) |
|
1141 |
(fp_line (start -1.905 4.445) (end -1.905 -4.445) (layer F.SilkS) (width 0.254)) |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
1142 |
(pad VI thru_hole circle (at 0 -2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
1143 |
(net 23 N-0000060)) |
|
1144 |
(pad GND thru_hole circle (at 0 0 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1145 |
(net 1 /GND)) |
|
1146 |
(pad VO thru_hole circle (at 0 2.54 90) (size 2.032 2.032) (drill 1.143) (layers *.Cu *.Mask F.SilkS) |
|
1147 |
(net 2 /VCC)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1148 |
) |
1149 |
||
|
50
by dan
finnished connecting all of the components together #=O) |
1150 |
(segment (start 31.75 67.31) (end 31.75 67.31) (width 0.381) (layer B.Cu) (net 0) (tstamp 534F2520)) |
1151 |
(segment (start 48.26 69.85) (end 52.07 73.66) (width 0.381) (layer B.Cu) (net 1)) |
|
1152 |
(segment (start 67.31 104.14) (end 67.31 109.22) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3283)) |
|
1153 |
(segment (start 68.58 102.87) (end 67.31 104.14) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3282)) |
|
1154 |
(segment (start 68.58 95.25) (end 68.58 102.87) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3281)) |
|
1155 |
(segment (start 71.12 92.71) (end 68.58 95.25) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F3280)) |
|
1156 |
(segment (start 71.12 80.01) (end 71.12 92.71) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327F)) |
|
1157 |
(segment (start 64.77 73.66) (end 71.12 80.01) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327E)) |
|
1158 |
(segment (start 52.07 73.66) (end 64.77 73.66) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F327D)) |
|
1159 |
(segment (start 48.26 115.57) (end 43.18 115.57) (width 0.381) (layer B.Cu) (net 1)) |
|
1160 |
(segment (start 43.18 115.57) (end 39.37 119.38) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2F0F)) |
|
1161 |
(segment (start 39.37 119.38) (end 36.83 119.38) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2F10)) |
|
1162 |
(segment (start 67.31 109.22) (end 68.58 109.22) (width 0.381) (layer B.Cu) (net 1)) |
|
1163 |
(segment (start 62.23 115.57) (end 48.26 115.57) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF6)) |
|
1164 |
(segment (start 64.77 113.03) (end 62.23 115.57) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF4)) |
|
1165 |
(segment (start 68.58 113.03) (end 64.77 113.03) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF3)) |
|
1166 |
(segment (start 69.85 111.76) (end 68.58 113.03) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF2)) |
|
1167 |
(segment (start 69.85 110.49) (end 69.85 111.76) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF1)) |
|
1168 |
(segment (start 68.58 109.22) (end 69.85 110.49) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EF0)) |
|
1169 |
(segment (start 36.83 110.49) (end 36.83 109.22) (width 0.381) (layer B.Cu) (net 1)) |
|
1170 |
(segment (start 36.83 109.22) (end 29.21 101.6) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE6)) |
|
1171 |
(segment (start 25.4 76.2) (end 26.67 76.2) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EED)) |
|
1172 |
(segment (start 24.13 77.47) (end 25.4 76.2) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEC)) |
|
1173 |
(segment (start 24.13 83.82) (end 24.13 77.47) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEB)) |
|
1174 |
(segment (start 25.4 85.09) (end 24.13 83.82) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EEA)) |
|
1175 |
(segment (start 27.94 85.09) (end 25.4 85.09) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE9)) |
|
1176 |
(segment (start 29.21 86.36) (end 27.94 85.09) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE8)) |
|
1177 |
(segment (start 29.21 101.6) (end 29.21 86.36) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2EE7)) |
|
1178 |
(segment (start 39.37 106.68) (end 39.37 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2B87)) |
|
1179 |
(segment (start 36.83 109.22) (end 39.37 106.68) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2B83)) |
|
1180 |
(segment (start 60.96 96.52) (end 60.96 93.98) (width 0.381) (layer B.Cu) (net 1)) |
|
1181 |
(segment (start 60.96 93.98) (end 60.96 91.44) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A13)) |
|
1182 |
(segment (start 60.96 91.44) (end 60.96 88.9) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A14)) |
|
1183 |
(segment (start 34.29 99.06) (end 36.83 99.06) (width 0.381) (layer B.Cu) (net 1)) |
|
1184 |
(segment (start 36.83 99.06) (end 39.37 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A06)) |
|
1185 |
(segment (start 39.37 99.06) (end 41.91 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A07)) |
|
1186 |
(segment (start 41.91 99.06) (end 44.45 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A08)) |
|
1187 |
(segment (start 44.45 99.06) (end 46.99 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A09)) |
|
1188 |
(segment (start 46.99 99.06) (end 49.53 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0A)) |
|
1189 |
(segment (start 49.53 99.06) (end 52.07 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0B)) |
|
1190 |
(segment (start 52.07 99.06) (end 54.61 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0C)) |
|
1191 |
(segment (start 54.61 99.06) (end 58.42 99.06) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0D)) |
|
1192 |
(segment (start 58.42 99.06) (end 60.96 96.52) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2A0E)) |
|
1193 |
(segment (start 36.83 114.3) (end 36.83 110.49) (width 0.381) (layer B.Cu) (net 1)) |
|
1194 |
(segment (start 45.72 69.85) (end 48.26 69.85) (width 0.381) (layer B.Cu) (net 1)) |
|
1195 |
(segment (start 43.18 80.01) (end 43.18 74.93) (width 0.381) (layer B.Cu) (net 1)) |
|
1196 |
(segment (start 45.72 72.39) (end 45.72 69.85) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F28F4)) |
|
1197 |
(segment (start 43.18 74.93) (end 45.72 72.39) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F28F1)) |
|
1198 |
(segment (start 30.48 73.66) (end 30.48 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2533)) |
|
1199 |
(segment (start 27.94 76.2) (end 30.48 73.66) (width 0.381) (layer B.Cu) (net 1) (tstamp 534F2531)) |
|
1200 |
(segment (start 26.67 76.2) (end 27.94 76.2) (width 0.381) (layer B.Cu) (net 1)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1201 |
(segment (start 38.1 64.77) (end 38.1 63.5) (width 0.381) (layer B.Cu) (net 1)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1202 |
(segment (start 31.75 62.23) (end 30.48 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C911D)) |
1203 |
(segment (start 36.83 62.23) (end 31.75 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C911B)) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
1204 |
(segment (start 38.1 63.5) (end 36.83 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9118)) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1205 |
(segment (start 30.48 57.15) (end 31.75 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9124)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1206 |
(segment (start 29.21 58.42) (end 30.48 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9122)) |
1207 |
(segment (start 29.21 60.96) (end 29.21 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9121)) |
|
|
49
by Tim Marston
mega-shield project: fixed-up two more tracks |
1208 |
(segment (start 30.48 62.23) (end 29.21 60.96) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C9120)) |
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1209 |
(segment (start 36.83 119.38) (end 36.83 114.3) (width 0.381) (layer B.Cu) (net 1)) |
1210 |
(segment (start 26.67 76.2) (end 26.67 73.66) (width 0.381) (layer B.Cu) (net 1)) |
|
1211 |
(segment (start 68.58 72.39) (end 67.31 72.39) (width 0.381) (layer B.Cu) (net 1)) |
|
1212 |
(segment (start 71.12 62.23) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8008)) |
|
1213 |
(segment (start 71.12 64.77) (end 71.12 62.23) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8003)) |
|
1214 |
(segment (start 69.85 66.04) (end 71.12 64.77) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8002)) |
|
1215 |
(segment (start 67.31 66.04) (end 69.85 66.04) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C8000)) |
|
1216 |
(segment (start 66.04 67.31) (end 67.31 66.04) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFF)) |
|
1217 |
(segment (start 66.04 71.12) (end 66.04 67.31) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFD)) |
|
1218 |
(segment (start 67.31 72.39) (end 66.04 71.12) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7FFB)) |
|
1219 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C800F)) |
|
1220 |
(segment (start 69.85 57.15) (end 71.12 57.15) (width 0.381) (layer B.Cu) (net 1)) |
|
1221 |
(segment (start 71.12 57.15) (end 72.39 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E0D)) |
|
1222 |
(segment (start 72.39 58.42) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E11)) |
|
1223 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E13)) |
|
1224 |
(segment (start 69.85 49.53) (end 71.12 49.53) (width 0.381) (layer B.Cu) (net 1)) |
|
1225 |
(segment (start 71.12 49.53) (end 72.39 50.8) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7DF5)) |
|
1226 |
(segment (start 72.39 50.8) (end 72.39 58.42) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E03)) |
|
1227 |
(segment (start 73.66 59.69) (end 74.93 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E09)) |
|
1228 |
(segment (start 72.39 58.42) (end 73.66 59.69) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7E08)) |
|
1229 |
(segment (start 31.75 57.15) (end 39.37 57.15) (width 0.381) (layer B.Cu) (net 1)) |
|
1230 |
(segment (start 39.37 57.15) (end 46.99 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A99)) |
|
1231 |
(segment (start 46.99 57.15) (end 54.61 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9B)) |
|
1232 |
(segment (start 54.61 57.15) (end 62.23 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9C)) |
|
1233 |
(segment (start 62.23 57.15) (end 69.85 57.15) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C7A9E)) |
|
1234 |
(segment (start 31.75 49.53) (end 39.37 49.53) (width 0.381) (layer B.Cu) (net 1)) |
|
1235 |
(segment (start 39.37 49.53) (end 46.99 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79E6)) |
|
1236 |
(segment (start 46.99 49.53) (end 54.61 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79E8)) |
|
1237 |
(segment (start 54.61 49.53) (end 62.23 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79EB)) |
|
1238 |
(segment (start 62.23 49.53) (end 69.85 49.53) (width 0.381) (layer B.Cu) (net 1) (tstamp 534C79EC)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1239 |
(segment (start 31.75 76.2) (end 40.64 67.31) (width 0.381) (layer B.Cu) (net 2)) |
1240 |
(segment (start 43.18 64.77) (end 40.64 67.31) (width 0.381) (layer B.Cu) (net 2)) |
|
1241 |
(segment (start 31.75 76.2) (end 29.21 78.74) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2524)) |
|
1242 |
(segment (start 29.21 78.74) (end 26.67 78.74) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F252A)) |
|
1243 |
(segment (start 63.5 88.9) (end 63.5 87.63) (width 0.381) (layer B.Cu) (net 2)) |
|
1244 |
(segment (start 62.23 86.36) (end 31.75 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EBF)) |
|
1245 |
(segment (start 63.5 87.63) (end 62.23 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EBE)) |
|
1246 |
(segment (start 63.5 96.52) (end 63.5 93.98) (width 0.381) (layer B.Cu) (net 2)) |
|
1247 |
(segment (start 63.5 93.98) (end 63.5 91.44) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA9)) |
|
1248 |
(segment (start 63.5 91.44) (end 63.5 88.9) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BAA)) |
|
1249 |
(segment (start 64.77 111.76) (end 64.77 106.68) (width 0.381) (layer B.Cu) (net 2)) |
|
1250 |
(segment (start 63.5 105.41) (end 63.5 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA5)) |
|
1251 |
(segment (start 64.77 106.68) (end 63.5 105.41) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2BA0)) |
|
1252 |
(segment (start 39.37 114.3) (end 41.91 114.3) (width 0.381) (layer B.Cu) (net 2)) |
|
1253 |
(segment (start 64.77 111.76) (end 67.31 111.76) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B6A)) |
|
1254 |
(segment (start 63.5 113.03) (end 64.77 111.76) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B69)) |
|
1255 |
(segment (start 43.18 113.03) (end 63.5 113.03) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B68)) |
|
1256 |
(segment (start 41.91 114.3) (end 43.18 113.03) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2B67)) |
|
1257 |
(segment (start 34.29 96.52) (end 36.83 96.52) (width 0.381) (layer B.Cu) (net 2)) |
|
1258 |
(segment (start 36.83 96.52) (end 39.37 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293C)) |
|
1259 |
(segment (start 39.37 96.52) (end 41.91 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293D)) |
|
1260 |
(segment (start 41.91 96.52) (end 44.45 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293E)) |
|
1261 |
(segment (start 44.45 96.52) (end 46.99 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F293F)) |
|
1262 |
(segment (start 46.99 96.52) (end 49.53 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2940)) |
|
1263 |
(segment (start 49.53 96.52) (end 52.07 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2941)) |
|
1264 |
(segment (start 52.07 96.52) (end 54.61 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2942)) |
|
1265 |
(segment (start 26.67 78.74) (end 26.67 80.01) (width 0.381) (layer B.Cu) (net 2)) |
|
1266 |
(segment (start 31.75 85.09) (end 31.75 86.36) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2931)) |
|
1267 |
(segment (start 26.67 80.01) (end 31.75 85.09) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F291D)) |
|
1268 |
(segment (start 31.75 93.98) (end 34.29 96.52) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2938)) |
|
1269 |
(segment (start 31.75 86.36) (end 31.75 93.98) (width 0.381) (layer B.Cu) (net 2) (tstamp 534F2EC2)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1270 |
(segment (start 43.18 64.77) (end 43.18 63.5) (width 0.381) (layer B.Cu) (net 2)) |
1271 |
(segment (start 43.18 63.5) (end 44.45 62.23) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8474)) |
|
1272 |
(segment (start 44.45 62.23) (end 45.72 62.23) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8476)) |
|
1273 |
(segment (start 46.99 60.96) (end 46.99 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8479)) |
|
1274 |
(segment (start 45.72 62.23) (end 46.99 60.96) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C8478)) |
|
1275 |
(segment (start 68.58 64.77) (end 68.58 62.23) (width 0.381) (layer B.Cu) (net 2)) |
|
1276 |
(segment (start 69.85 60.96) (end 69.85 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7FF8)) |
|
1277 |
(segment (start 68.58 62.23) (end 69.85 60.96) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7FF7)) |
|
1278 |
(segment (start 31.75 59.69) (end 39.37 59.69) (width 0.381) (layer B.Cu) (net 2)) |
|
1279 |
(segment (start 39.37 59.69) (end 46.99 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA5)) |
|
1280 |
(segment (start 46.99 59.69) (end 54.61 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA6)) |
|
1281 |
(segment (start 54.61 59.69) (end 62.23 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA7)) |
|
1282 |
(segment (start 62.23 59.69) (end 69.85 59.69) (width 0.381) (layer B.Cu) (net 2) (tstamp 534C7AA8)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1283 |
(segment (start 50.8 80.01) (end 50.8 78.74) (width 0.381) (layer B.Cu) (net 3)) |
1284 |
(segment (start 69.85 92.71) (end 66.04 96.52) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F29A7)) |
|
1285 |
(segment (start 69.85 80.01) (end 69.85 92.71) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F29A1)) |
|
1286 |
(segment (start 64.77 74.93) (end 69.85 80.01) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F299C)) |
|
1287 |
(segment (start 54.61 74.93) (end 64.77 74.93) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F299A)) |
|
1288 |
(segment (start 50.8 78.74) (end 54.61 74.93) (width 0.381) (layer B.Cu) (net 3) (tstamp 534F2999)) |
|
1289 |
(segment (start 48.26 77.47) (end 48.26 80.01) (width 0.381) (layer B.Cu) (net 4)) |
|
1290 |
(segment (start 49.53 83.82) (end 49.53 82.55) (width 0.381) (layer B.Cu) (net 4)) |
|
1291 |
(segment (start 48.26 81.28) (end 48.26 80.01) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28EB)) |
|
1292 |
(segment (start 49.53 82.55) (end 48.26 81.28) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E7)) |
|
1293 |
(segment (start 44.45 83.82) (end 46.99 83.82) (width 0.381) (layer B.Cu) (net 4)) |
|
1294 |
(segment (start 46.99 83.82) (end 49.53 83.82) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E1)) |
|
1295 |
(segment (start 49.53 83.82) (end 52.07 83.82) (width 0.381) (layer B.Cu) (net 4) (tstamp 534F28E3)) |
|
1296 |
(segment (start 52.07 91.44) (end 52.07 93.98) (width 0.381) (layer B.Cu) (net 5)) |
|
1297 |
(segment (start 49.53 91.44) (end 49.53 93.98) (width 0.381) (layer B.Cu) (net 6)) |
|
1298 |
(segment (start 53.34 80.01) (end 53.34 78.74) (width 0.381) (layer B.Cu) (net 7)) |
|
1299 |
(segment (start 68.58 91.44) (end 66.04 93.98) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F298F)) |
|
1300 |
(segment (start 68.58 80.01) (end 68.58 91.44) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F298C)) |
|
1301 |
(segment (start 64.77 76.2) (end 68.58 80.01) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2989)) |
|
1302 |
(segment (start 55.88 76.2) (end 64.77 76.2) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2987)) |
|
1303 |
(segment (start 53.34 78.74) (end 55.88 76.2) (width 0.381) (layer B.Cu) (net 7) (tstamp 534F2986)) |
|
1304 |
(segment (start 46.99 91.44) (end 46.99 93.98) (width 0.381) (layer B.Cu) (net 8)) |
|
1305 |
(segment (start 44.45 91.44) (end 44.45 93.98) (width 0.381) (layer B.Cu) (net 9)) |
|
1306 |
(segment (start 39.37 91.44) (end 39.37 93.98) (width 0.381) (layer B.Cu) (net 10)) |
|
1307 |
(segment (start 36.83 91.44) (end 36.83 93.98) (width 0.381) (layer B.Cu) (net 11)) |
|
1308 |
(segment (start 45.72 77.47) (end 45.72 80.01) (width 0.381) (layer B.Cu) (net 12)) |
|
1309 |
(segment (start 34.29 83.82) (end 36.83 83.82) (width 0.381) (layer B.Cu) (net 12)) |
|
1310 |
(segment (start 36.83 83.82) (end 39.37 83.82) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28D8)) |
|
1311 |
(segment (start 39.37 83.82) (end 41.91 83.82) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28D9)) |
|
1312 |
(segment (start 41.91 83.82) (end 45.72 80.01) (width 0.381) (layer B.Cu) (net 12) (tstamp 534F28DA)) |
|
1313 |
(segment (start 41.91 91.44) (end 41.91 93.98) (width 0.381) (layer B.Cu) (net 13)) |
|
1314 |
(segment (start 34.29 91.44) (end 34.29 93.98) (width 0.381) (layer B.Cu) (net 14)) |
|
1315 |
(segment (start 55.88 80.01) (end 55.88 78.74) (width 0.381) (layer B.Cu) (net 15)) |
|
1316 |
(segment (start 67.31 90.17) (end 66.04 91.44) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F2982)) |
|
1317 |
(segment (start 67.31 80.01) (end 67.31 90.17) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297F)) |
|
1318 |
(segment (start 64.77 77.47) (end 67.31 80.01) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297B)) |
|
1319 |
(segment (start 57.15 77.47) (end 64.77 77.47) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F297A)) |
|
1320 |
(segment (start 55.88 78.74) (end 57.15 77.47) (width 0.381) (layer B.Cu) (net 15) (tstamp 534F2979)) |
|
1321 |
(segment (start 73.66 91.44) (end 73.66 92.71) (width 0.381) (layer B.Cu) (net 16)) |
|
1322 |
(segment (start 35.56 74.93) (end 43.18 67.31) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EAE)) |
|
1323 |
(segment (start 43.18 67.31) (end 50.8 67.31) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EAF)) |
|
1324 |
(segment (start 50.8 67.31) (end 54.61 71.12) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB0)) |
|
1325 |
(segment (start 54.61 71.12) (end 64.77 71.12) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB2)) |
|
1326 |
(segment (start 64.77 71.12) (end 73.66 80.01) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB4)) |
|
1327 |
(segment (start 73.66 80.01) (end 73.66 91.44) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB6)) |
|
1328 |
(segment (start 72.39 93.98) (end 72.39 113.03) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EB9)) |
|
1329 |
(segment (start 72.39 113.03) (end 73.66 114.3) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EBA)) |
|
1330 |
(segment (start 74.93 114.3) (end 73.66 114.3) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F2EBB)) |
|
1331 |
(segment (start 35.56 74.93) (end 35.56 80.01) (width 0.381) (layer B.Cu) (net 16)) |
|
1332 |
(segment (start 73.66 92.71) (end 72.39 93.98) (width 0.381) (layer B.Cu) (net 16) (tstamp 534F3272)) |
|
1333 |
(segment (start 58.42 80.01) (end 59.69 78.74) (width 0.381) (layer B.Cu) (net 17)) |
|
1334 |
(segment (start 66.04 80.01) (end 66.04 88.9) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2976)) |
|
1335 |
(segment (start 64.77 78.74) (end 66.04 80.01) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2975)) |
|
1336 |
(segment (start 59.69 78.74) (end 64.77 78.74) (width 0.381) (layer B.Cu) (net 17) (tstamp 534F2974)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1337 |
(segment (start 68.58 67.31) (end 69.85 67.31) (width 0.381) (layer B.Cu) (net 18)) |
1338 |
(segment (start 73.66 62.23) (end 74.93 62.23) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8017)) |
|
1339 |
(segment (start 72.39 63.5) (end 73.66 62.23) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8015)) |
|
1340 |
(segment (start 72.39 64.77) (end 72.39 63.5) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8013)) |
|
1341 |
(segment (start 69.85 67.31) (end 72.39 64.77) (width 0.381) (layer B.Cu) (net 18) (tstamp 534C8012)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1342 |
(segment (start 38.1 80.01) (end 38.1 74.93) (width 0.381) (layer B.Cu) (net 19)) |
1343 |
(segment (start 76.2 111.76) (end 74.93 111.76) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EAB)) |
|
1344 |
(segment (start 77.47 113.03) (end 76.2 111.76) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EAA)) |
|
1345 |
(segment (start 77.47 114.3) (end 77.47 113.03) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA9)) |
|
1346 |
(segment (start 76.2 115.57) (end 77.47 114.3) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA8)) |
|
1347 |
(segment (start 72.39 115.57) (end 76.2 115.57) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA7)) |
|
1348 |
(segment (start 71.12 114.3) (end 72.39 115.57) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA6)) |
|
1349 |
(segment (start 71.12 93.98) (end 71.12 114.3) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA5)) |
|
1350 |
(segment (start 72.39 92.71) (end 71.12 93.98) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA4)) |
|
1351 |
(segment (start 72.39 80.01) (end 72.39 92.71) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA2)) |
|
1352 |
(segment (start 64.77 72.39) (end 72.39 80.01) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2EA0)) |
|
1353 |
(segment (start 53.34 72.39) (end 64.77 72.39) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9E)) |
|
1354 |
(segment (start 49.53 68.58) (end 53.34 72.39) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9C)) |
|
1355 |
(segment (start 44.45 68.58) (end 49.53 68.58) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E9A)) |
|
1356 |
(segment (start 38.1 74.93) (end 44.45 68.58) (width 0.381) (layer B.Cu) (net 19) (tstamp 534F2E98)) |
|
1357 |
(segment (start 67.31 114.3) (end 69.85 114.3) (width 0.381) (layer B.Cu) (net 20)) |
|
1358 |
(segment (start 72.39 116.84) (end 74.93 116.84) (width 0.381) (layer B.Cu) (net 20) (tstamp 534F2BC1)) |
|
1359 |
(segment (start 69.85 114.3) (end 72.39 116.84) (width 0.381) (layer B.Cu) (net 20) (tstamp 534F2BC0)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1360 |
(segment (start 68.58 69.85) (end 69.85 69.85) (width 0.381) (layer B.Cu) (net 21)) |
1361 |
(segment (start 69.85 69.85) (end 74.93 64.77) (width 0.381) (layer B.Cu) (net 21) (tstamp 534C801B)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1362 |
(segment (start 67.31 116.84) (end 69.85 116.84) (width 0.381) (layer B.Cu) (net 22)) |
1363 |
(segment (start 72.39 119.38) (end 74.93 119.38) (width 0.381) (layer B.Cu) (net 22) (tstamp 534F2BBC)) |
|
1364 |
(segment (start 69.85 116.84) (end 72.39 119.38) (width 0.381) (layer B.Cu) (net 22) (tstamp 534F2BB8)) |
|
1365 |
(segment (start 25.4 72.39) (end 24.13 73.66) (width 0.381) (layer B.Cu) (net 23)) |
|
1366 |
(segment (start 29.21 109.22) (end 29.21 106.68) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C844E)) |
|
1367 |
(segment (start 29.21 106.68) (end 29.21 105.41) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C844F)) |
|
1368 |
(segment (start 29.21 105.41) (end 27.94 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8450)) |
|
1369 |
(segment (start 27.94 104.14) (end 25.4 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8451)) |
|
1370 |
(segment (start 25.4 72.39) (end 27.94 72.39) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8455)) |
|
1371 |
(segment (start 27.94 72.39) (end 29.21 71.12) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8456)) |
|
1372 |
(segment (start 29.21 71.12) (end 29.21 64.77) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8458)) |
|
1373 |
(segment (start 29.21 64.77) (end 27.94 63.5) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8459)) |
|
1374 |
(segment (start 27.94 63.5) (end 27.94 53.34) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845A)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1375 |
(segment (start 27.94 53.34) (end 29.21 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845B)) |
|
50
by dan
finnished connecting all of the components together #=O) |
1376 |
(segment (start 31.75 52.07) (end 29.21 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845C)) |
1377 |
(segment (start 29.21 109.22) (end 34.29 114.3) (width 0.381) (layer B.Cu) (net 23)) |
|
1378 |
(segment (start 24.13 102.87) (end 25.4 104.14) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1D)) |
|
1379 |
(segment (start 24.13 85.09) (end 24.13 102.87) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1C)) |
|
1380 |
(segment (start 22.86 83.82) (end 24.13 85.09) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1B)) |
|
1381 |
(segment (start 22.86 77.47) (end 22.86 83.82) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F1A)) |
|
1382 |
(segment (start 24.13 76.2) (end 22.86 77.47) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F19)) |
|
1383 |
(segment (start 24.13 74.93) (end 24.13 76.2) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F18)) |
|
1384 |
(segment (start 24.13 73.66) (end 24.13 74.93) (width 0.381) (layer B.Cu) (net 23) (tstamp 534F2F17)) |
|
1385 |
(segment (start 34.29 114.3) (end 34.29 110.49) (width 0.381) (layer B.Cu) (net 23)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1386 |
(segment (start 31.75 52.07) (end 39.37 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845D)) |
1387 |
(segment (start 39.37 52.07) (end 46.99 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845E)) |
|
1388 |
(segment (start 46.99 52.07) (end 54.61 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C845F)) |
|
1389 |
(segment (start 54.61 52.07) (end 62.23 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8460)) |
|
1390 |
(segment (start 62.23 52.07) (end 69.85 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C8461)) |
|
1391 |
(segment (start 34.29 119.38) (end 34.29 114.3) (width 0.381) (layer B.Cu) (net 23)) |
|
1392 |
(segment (start 31.75 52.07) (end 39.37 52.07) (width 0.381) (layer B.Cu) (net 23)) |
|
1393 |
(segment (start 39.37 52.07) (end 46.99 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FC)) |
|
1394 |
(segment (start 46.99 52.07) (end 54.61 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FD)) |
|
1395 |
(segment (start 54.61 52.07) (end 62.23 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FE)) |
|
1396 |
(segment (start 62.23 52.07) (end 69.85 52.07) (width 0.381) (layer B.Cu) (net 23) (tstamp 534C79FF)) |
|
|
50
by dan
finnished connecting all of the components together #=O) |
1397 |
(segment (start 34.29 102.87) (end 30.48 99.06) (width 0.381) (layer B.Cu) (net 24)) |
1398 |
(segment (start 27.94 83.82) (end 26.67 83.82) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A6F)) |
|
1399 |
(segment (start 30.48 86.36) (end 27.94 83.82) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A6C)) |
|
1400 |
(segment (start 30.48 99.06) (end 30.48 86.36) (width 0.381) (layer B.Cu) (net 24) (tstamp 534F2A68)) |
|
1401 |
(segment (start 34.29 102.87) (end 36.83 102.87) (width 0.381) (layer B.Cu) (net 24)) |
|
|
47
by dan
First attempt at connecting up all the components on the circuit. Almost finnished but not managed to connect scl, sda, tx0 & rx0. Gonna pass over to Tim to see if he can find a solution. |
1402 |
(segment (start 74.93 57.15) (end 74.93 48.26) (width 0.381) (layer B.Cu) (net 25)) |
1403 |
(segment (start 25.4 71.12) (end 26.67 71.12) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A6F)) |
|
1404 |
(segment (start 24.13 69.85) (end 25.4 71.12) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A6E)) |
|
1405 |
(segment (start 24.13 63.5) (end 24.13 69.85) (width 0.381) (layer B.Cu) (net 25) (tstamp 534C7A64)) |
|
1406 |
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|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1411 |
|
|
59
by dan
Modified Schimatic to incorperate pin out for Serial 3 and freed up serial 1 (for use as interupt) |
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|
1883 |
(xy 39.497 49.677) (xy 39.243 49.677) (xy 39.243 49.657) (xy 37.75728 49.657) (xy 37.63478 49.87307) |
|
1884 |
(xy 37.64974 49.947277) (xy 37.91137 50.428026) (xy 38.337059 50.772059) (xy 38.401839 50.791179) (xy 37.966339 51.082172) |
|
1885 |
(xy 37.857875 51.2445) (xy 33.262125 51.2445) (xy 33.153661 51.082172) (xy 32.718161 50.791179) (xy 32.782941 50.772059) |
|
1886 |
(xy 33.20863 50.428026) (xy 33.47026 49.947277) (xy 33.48522 49.87307) (xy 33.36272 49.657) (xy 31.877 49.657) |
|
1887 |
(xy 31.877 49.677) (xy 31.623 49.677) (xy 31.623 49.657) (xy 30.13728 49.657) (xy 30.01478 49.87307) |
|
1888 |
(xy 30.02974 49.947277) (xy 30.29137 50.428026) (xy 30.717059 50.772059) (xy 30.781839 50.791179) (xy 30.346339 51.082172) |
|
1889 |
(xy 30.237875 51.2445) (xy 29.21 51.2445) (xy 28.894094 51.307337) (xy 28.786824 51.379013) (xy 28.626283 51.486283) |
|
1890 |
(xy 28.626281 51.486286) (xy 27.4955 52.617066) (xy 27.4955 49.18693) (xy 30.01478 49.18693) (xy 30.13728 49.403) |
|
1891 |
(xy 31.623 49.403) (xy 31.623 48.133) (xy 31.877 48.133) (xy 31.877 49.403) (xy 33.36272 49.403) |
|
1892 |
(xy 33.48522 49.18693) (xy 37.63478 49.18693) (xy 37.75728 49.403) (xy 39.243 49.403) (xy 39.243 48.133) |
|
1893 |
(xy 39.497 48.133) (xy 39.497 49.403) (xy 40.98272 49.403) (xy 41.10522 49.18693) (xy 45.25478 49.18693) |
|
1894 |
(xy 45.37728 49.403) (xy 46.863 49.403) (xy 46.863 48.133) (xy 47.117 48.133) (xy 47.117 49.403) |
|
1895 |
(xy 48.60272 49.403) (xy 48.72522 49.18693) (xy 52.87478 49.18693) (xy 52.99728 49.403) (xy 54.483 49.403) |
|
1896 |
(xy 54.483 48.133) (xy 54.737 48.133) (xy 54.737 49.403) (xy 56.22272 49.403) (xy 56.34522 49.18693) |
|
1897 |
(xy 60.49478 49.18693) (xy 60.61728 49.403) (xy 62.103 49.403) (xy 62.103 48.133) (xy 62.357 48.133) |
|
1898 |
(xy 62.357 49.403) (xy 63.84272 49.403) (xy 63.96522 49.18693) (xy 68.11478 49.18693) (xy 68.23728 49.403) |
|
1899 |
(xy 69.723 49.403) (xy 69.723 48.133) (xy 69.977 48.133) (xy 69.977 49.403) (xy 71.46272 49.403) |
|
1900 |
(xy 71.58522 49.18693) (xy 71.57026 49.112723) (xy 71.30863 48.631974) (xy 70.882941 48.287941) (xy 70.358 48.133) |
|
1901 |
(xy 69.977 48.133) (xy 69.723 48.133) (xy 69.342 48.133) (xy 68.817059 48.287941) (xy 68.39137 48.631974) |
|
1902 |
(xy 68.12974 49.112723) (xy 68.11478 49.18693) (xy 63.96522 49.18693) (xy 63.95026 49.112723) (xy 63.68863 48.631974) |
|
1903 |
(xy 63.262941 48.287941) (xy 62.738 48.133) (xy 62.357 48.133) (xy 62.103 48.133) (xy 61.722 48.133) |
|
1904 |
(xy 61.197059 48.287941) (xy 60.77137 48.631974) (xy 60.50974 49.112723) (xy 60.49478 49.18693) (xy 56.34522 49.18693) |
|
1905 |
(xy 56.33026 49.112723) (xy 56.06863 48.631974) (xy 55.642941 48.287941) (xy 55.118 48.133) (xy 54.737 48.133) |
|
1906 |
(xy 54.483 48.133) (xy 54.102 48.133) (xy 53.577059 48.287941) (xy 53.15137 48.631974) (xy 52.88974 49.112723) |
|
1907 |
(xy 52.87478 49.18693) (xy 48.72522 49.18693) (xy 48.71026 49.112723) (xy 48.44863 48.631974) (xy 48.022941 48.287941) |
|
1908 |
(xy 47.498 48.133) (xy 47.117 48.133) (xy 46.863 48.133) (xy 46.482 48.133) (xy 45.957059 48.287941) |
|
1909 |
(xy 45.53137 48.631974) (xy 45.26974 49.112723) (xy 45.25478 49.18693) (xy 41.10522 49.18693) (xy 41.09026 49.112723) |
|
1910 |
(xy 40.82863 48.631974) (xy 40.402941 48.287941) (xy 39.878 48.133) (xy 39.497 48.133) (xy 39.243 48.133) |
|
1911 |
(xy 38.862 48.133) (xy 38.337059 48.287941) (xy 37.91137 48.631974) (xy 37.64974 49.112723) (xy 37.63478 49.18693) |
|
1912 |
(xy 33.48522 49.18693) (xy 33.47026 49.112723) (xy 33.20863 48.631974) (xy 32.782941 48.287941) (xy 32.258 48.133) |
|
1913 |
(xy 31.877 48.133) (xy 31.623 48.133) (xy 31.242 48.133) (xy 30.717059 48.287941) (xy 30.29137 48.631974) |
|
1914 |
(xy 30.02974 49.112723) (xy 30.01478 49.18693) (xy 27.4955 49.18693) (xy 27.4955 48.601934) (xy 28.281933 47.8155) |
|
1915 |
(xy 73.318066 47.8155) (xy 74.1045 48.601933) (xy 74.1045 55.704705) (xy 73.996005 55.749534) (xy 73.531166 56.213563) |
|
1916 |
(xy 73.279287 56.820155) (xy 73.278714 57.476963) (xy 73.529534 58.083995) (xy 73.952366 58.507565) (xy 73.945498 58.525893) |
|
1917 |
(xy 74.93 59.510395) (xy 75.914502 58.525893) (xy 75.907453 58.507083) (xy 76.328834 58.086437) (xy 76.580713 57.479845) |
|
1918 |
(xy 76.581286 56.823037) (xy 76.330466 56.216005) (xy 75.866437 55.751166) (xy 75.7555 55.705101) (xy 75.7555 48.26) |
|
1919 |
(xy 75.692663 47.944095) (xy 75.692663 47.944094) (xy 75.564752 47.752663) (xy 75.513717 47.676283) (xy 75.513714 47.676281) |
|
1920 |
(xy 74.243717 46.406283) (xy 73.975906 46.227337) (xy 73.66 46.1645) (xy 27.94 46.1645) (xy 27.624094 46.227337) |
|
1921 |
(xy 27.516824 46.299013) (xy 27.356283 46.406283) (xy 27.356281 46.406286) (xy 26.086283 47.676283) (xy 25.907337 47.944094) |
|
1922 |
(xy 25.907337 47.944095) (xy 25.8445 48.26) (xy 25.8445 60.618067) (xy 23.546283 62.916283) (xy 23.367337 63.184094) |
|
1923 |
(xy 23.3045 63.5) (xy 23.3045 69.85) (xy 23.367337 70.165906) (xy 23.546283 70.433717) (xy 24.816281 71.703714) |
|
1924 |
(xy 24.816283 71.703717) (xy 24.893034 71.755) (xy 24.816283 71.806283) (xy 24.816281 71.806286) (xy 23.546283 73.076283) |
|
1925 |
(xy 23.367337 73.344094) (xy 23.329762 73.533) (xy 23.3045 73.66) (xy 23.3045 75.858067) (xy 22.276283 76.886283) |
|
1926 |
(xy 22.097337 77.154094) (xy 22.055563 77.364107) (xy 22.0345 77.47) (xy 21.717 77.47) (xy 21.717 44.577) |
|
1927 |
(xy 78.613 44.577) |
|
1928 |
) |
|
1929 |
) |
|
1930 |
) |
|
|
46
by dan
Added the pcb layout (mega-shield.kicad_pcb) although it is unfinnished at this stage! |
1931 |
) |